| /external/llvm/utils/TableGen/ |
| X86RecognizableInstr.h | 51 /// The OpSize field from the record
52 uint8_t OpSize;
118 /// @param OpSize Indicates the operand size of the instruction.
119 /// If register size does not match OpSize, then
123 bool hasREX_WPrefix, uint8_t OpSize);
130 /// @param OpSize - Indicates whether this is an OpSize16 instruction.
134 uint8_t OpSize);
139 uint8_t OpSize);
144 uint8_t OpSize);
146 uint8_t OpSize);
[all...] |
| X86RecognizableInstr.cpp | 194 OpSize = byteFromRec(Rec, "OpSizeBits");
402 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
404 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
406 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
408 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
425 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
427 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
429 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
450 uint8_t OpSize)) {
468 OpSize);
[all...] |
| /art/compiler/dex/quick/arm/ |
| codegen_arm.h | 36 OpSize size, VolatileKind is_volatile) OVERRIDE;
38 OpSize size) OVERRIDE;
42 OpSize size, VolatileKind is_volatile) OVERRIDE;
44 OpSize size) OVERRIDE;
84 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
91 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
93 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
109 bool GenInlinedPeek(CallInfo* info, OpSize size);
110 bool GenInlinedPoke(CallInfo* info, OpSize size);
164 LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size)
[all...] |
| utility_arm.cc | 693 int scale, OpSize size) {
759 int scale, OpSize size) {
855 OpSize size) {
966 OpSize size, VolatileKind is_volatile) {
996 OpSize size) {
[all...] |
| int_arm.cc | 751 bool ArmMir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) {
776 bool ArmMir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) {
[all...] |
| target_arm.cc | 541 RegisterClass ArmMir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) {
|
| /art/compiler/dex/quick/mips/ |
| codegen_mips.h | 36 OpSize size, VolatileKind is_volatile) OVERRIDE;
38 OpSize size) OVERRIDE;
42 OpSize size, VolatileKind is_volatile) OVERRIDE;
44 OpSize size) OVERRIDE;
84 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
89 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
91 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
107 bool GenInlinedPeek(CallInfo* info, OpSize size);
108 bool GenInlinedPoke(CallInfo* info, OpSize size);
163 OpSize size)
[all...] |
| utility_mips.cc | 357 int scale, OpSize size) {
410 int scale, OpSize size) {
456 OpSize size) {
553 OpSize size, VolatileKind is_volatile) {
575 RegStorage r_src, OpSize size) {
656 OpSize size, VolatileKind is_volatile) {
|
| int_mips.cc | 296 bool MipsMir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) {
312 bool MipsMir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) {
485 void MipsMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
554 void MipsMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
|
| target_mips.cc | 562 RegisterClass MipsMir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) {
|
| /art/compiler/dex/quick/arm64/ |
| codegen_arm64.h | 76 OpSize size, VolatileKind is_volatile) OVERRIDE;
80 OpSize size) OVERRIDE;
85 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,
90 OpSize size) OVERRIDE;
137 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
144 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
146 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
157 bool GenInlinedReverseBits(CallInfo* info, OpSize size) OVERRIDE;
168 bool GenInlinedPeek(CallInfo* info, OpSize size) OVERRIDE;
169 bool GenInlinedPoke(CallInfo* info, OpSize size) OVERRIDE
[all...] |
| utility_arm64.cc | [all...] |
| target_arm64.cc | 570 RegisterClass Arm64Mir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) {
859 OpSize* op_size) {
940 OpSize op_size;
[all...] |
| int_arm64.cc | 673 bool Arm64Mir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) {
689 bool Arm64Mir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) {
[all...] |
| /art/compiler/dex/quick/x86/ |
| codegen_x86.h | 73 OpSize size, VolatileKind is_volatile) OVERRIDE;
75 OpSize size) OVERRIDE;
79 OpSize size, VolatileKind is_volatile) OVERRIDE;
81 OpSize size) OVERRIDE;
143 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
146 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
148 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
165 bool GenInlinedPeek(CallInfo* info, OpSize size) OVERRIDE;
166 bool GenInlinedPoke(CallInfo* info, OpSize size) OVERRIDE;
411 RegStorage r_dest, OpSize size)
[all...] |
| target_x86.cc | 698 OpSize size = cu_->target64 ? k64 : k32;
715 OpSize size = cu_->target64 ? k64 : k32;
759 RegisterClass X86Mir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) {
1880 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); local
1910 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); local
1941 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); local
2021 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); local
2049 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); local
2074 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); local
2143 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); local
2236 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); local
2277 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); local
[all...] |
| utility_x86.cc | 635 int displacement, RegStorage r_dest, OpSize size) {
762 int scale, OpSize size) {
767 OpSize size, VolatileKind is_volatile) {
782 int displacement, RegStorage r_src, OpSize size) {
866 int scale, OpSize size) {
870 LIR* X86Mir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,
[all...] |
| /art/compiler/dex/quick/ |
| mir_to_lir.h | 592 RegisterClass RegClassBySize(OpSize size) {
[all...] |
| dex_file_method_inliner.cc | 443 return backend->GenInlinedReverseBytes(info, static_cast<OpSize>(intrinsic.d.data));
445 return backend->GenInlinedReverseBits(info, static_cast<OpSize>(intrinsic.d.data));
488 return backend->GenInlinedPeek(info, static_cast<OpSize>(intrinsic.d.data));
490 return backend->GenInlinedPoke(info, static_cast<OpSize>(intrinsic.d.data));
[all...] |
| gen_common.cc | 535 OpSize store_size = LoadStoreOpSize(is_long_or_double, is_object);
624 OpSize load_size = LoadStoreOpSize(is_long_or_double, is_object);
722 void Mir2Lir::GenIGet(MIR* mir, int opt_flags, OpSize size,
727 OpSize load_size = LoadStoreOpSize(is_long_or_double, is_object);
769 void Mir2Lir::GenIPut(MIR* mir, int opt_flags, OpSize size,
774 OpSize store_size = LoadStoreOpSize(is_long_or_double, is_object);
[all...] |
| mir_to_lir.cc | 238 OpSize size = LoadStoreOpSize(wide, ref);
282 OpSize size = LoadStoreOpSize(wide, ref);
[all...] |
| /art/compiler/dex/ |
| compiler_enums.h | 126 // It is encoded as OpSize << 16 | (number of bits in vector)
262 enum OpSize {
275 std::ostream& operator<<(std::ostream& os, const OpSize& kind);
|
| /external/llvm/lib/Analysis/ |
| TargetTransformInfo.cpp | 291 unsigned OpSize = OpTy->getScalarSizeInBits();
292 if (DL->isLegalInteger(OpSize) &&
293 OpSize <= DL->getPointerTypeSizeInBits(Ty))
|
| ConstantFolding.cpp | 656 unsigned OpSize = DL->getTypeSizeInBits(Op0->getType());
661 return ConstantInt::get(Op0->getType(), Offs1.zextOrTrunc(OpSize) -
662 Offs2.zextOrTrunc(OpSize));
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | [all...] |
