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      1 /*
      2  * Intel XScale PXA255/270 processor support.
      3  *
      4  * Copyright (c) 2006 Openedhand Ltd.
      5  * Written by Andrzej Zaborowski <balrog (at) zabor.org>
      6  *
      7  * This code is licenced under the GNU GPL v2.
      8  */
      9 #ifndef PXA_H
     10 # define PXA_H			"hw/arm/pxa.h"
     11 
     12 #include "cpu.h"
     13 
     14 /* Interrupt numbers */
     15 # define PXA2XX_PIC_SSP3	0
     16 # define PXA2XX_PIC_USBH2	2
     17 # define PXA2XX_PIC_USBH1	3
     18 # define PXA2XX_PIC_KEYPAD	4
     19 # define PXA2XX_PIC_PWRI2C	6
     20 # define PXA25X_PIC_HWUART	7
     21 # define PXA27X_PIC_OST_4_11	7
     22 # define PXA2XX_PIC_GPIO_0	8
     23 # define PXA2XX_PIC_GPIO_1	9
     24 # define PXA2XX_PIC_GPIO_X	10
     25 # define PXA2XX_PIC_I2S 	13
     26 # define PXA26X_PIC_ASSP	15
     27 # define PXA25X_PIC_NSSP	16
     28 # define PXA27X_PIC_SSP2	16
     29 # define PXA2XX_PIC_LCD		17
     30 # define PXA2XX_PIC_I2C		18
     31 # define PXA2XX_PIC_ICP		19
     32 # define PXA2XX_PIC_STUART	20
     33 # define PXA2XX_PIC_BTUART	21
     34 # define PXA2XX_PIC_FFUART	22
     35 # define PXA2XX_PIC_MMC		23
     36 # define PXA2XX_PIC_SSP		24
     37 # define PXA2XX_PIC_DMA		25
     38 # define PXA2XX_PIC_OST_0	26
     39 # define PXA2XX_PIC_RTC1HZ	30
     40 # define PXA2XX_PIC_RTCALARM	31
     41 
     42 /* DMA requests */
     43 # define PXA2XX_RX_RQ_I2S	2
     44 # define PXA2XX_TX_RQ_I2S	3
     45 # define PXA2XX_RX_RQ_BTUART	4
     46 # define PXA2XX_TX_RQ_BTUART	5
     47 # define PXA2XX_RX_RQ_FFUART	6
     48 # define PXA2XX_TX_RQ_FFUART	7
     49 # define PXA2XX_RX_RQ_SSP1	13
     50 # define PXA2XX_TX_RQ_SSP1	14
     51 # define PXA2XX_RX_RQ_SSP2	15
     52 # define PXA2XX_TX_RQ_SSP2	16
     53 # define PXA2XX_RX_RQ_ICP	17
     54 # define PXA2XX_TX_RQ_ICP	18
     55 # define PXA2XX_RX_RQ_STUART	19
     56 # define PXA2XX_TX_RQ_STUART	20
     57 # define PXA2XX_RX_RQ_MMCI	21
     58 # define PXA2XX_TX_RQ_MMCI	22
     59 # define PXA2XX_USB_RQ(x)	((x) + 24)
     60 # define PXA2XX_RX_RQ_SSP3	66
     61 # define PXA2XX_TX_RQ_SSP3	67
     62 
     63 # define PXA2XX_SDRAM_BASE	0xa0000000
     64 # define PXA2XX_INTERNAL_BASE	0x5c000000
     65 # define PXA2XX_INTERNAL_SIZE	0x40000
     66 
     67 /* pxa2xx_pic.c */
     68 qemu_irq *pxa2xx_pic_init(hwaddr base, CPUOldState *env);
     69 
     70 /* pxa2xx_timer.c */
     71 void pxa25x_timer_init(hwaddr base, qemu_irq *irqs);
     72 void pxa27x_timer_init(hwaddr base, qemu_irq *irqs, qemu_irq irq4);
     73 
     74 /* pxa2xx_gpio.c */
     75 typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
     76 PXA2xxGPIOInfo *pxa2xx_gpio_init(hwaddr base,
     77                 CPUOldState *env, qemu_irq *pic, int lines);
     78 qemu_irq *pxa2xx_gpio_in_get(PXA2xxGPIOInfo *s);
     79 void pxa2xx_gpio_out_set(PXA2xxGPIOInfo *s,
     80                 int line, qemu_irq handler);
     81 void pxa2xx_gpio_read_notifier(PXA2xxGPIOInfo *s, qemu_irq handler);
     82 
     83 /* pxa2xx_dma.c */
     84 typedef struct PXA2xxDMAState PXA2xxDMAState;
     85 PXA2xxDMAState *pxa255_dma_init(hwaddr base,
     86                 qemu_irq irq);
     87 PXA2xxDMAState *pxa27x_dma_init(hwaddr base,
     88                 qemu_irq irq);
     89 void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on);
     90 
     91 /* pxa2xx_lcd.c */
     92 typedef struct PXA2xxLCDState PXA2xxLCDState;
     93 PXA2xxLCDState *pxa2xx_lcdc_init(hwaddr base,
     94                 qemu_irq irq);
     95 void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
     96 void pxa2xx_lcdc_oritentation(void *opaque, int angle);
     97 
     98 /* pxa2xx_mmci.c */
     99 typedef struct PXA2xxMMCIState PXA2xxMMCIState;
    100 PXA2xxMMCIState *pxa2xx_mmci_init(hwaddr base,
    101                 BlockDriverState *bd, qemu_irq irq, void *dma);
    102 void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
    103                 qemu_irq coverswitch);
    104 
    105 /* pxa2xx_pcmcia.c */
    106 typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
    107 PXA2xxPCMCIAState *pxa2xx_pcmcia_init(hwaddr base);
    108 int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
    109 int pxa2xx_pcmcia_dettach(void *opaque);
    110 void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
    111 
    112 /* pxa2xx_keypad.c */
    113 struct  keymap {
    114     int column;
    115     int row;
    116 };
    117 typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
    118 PXA2xxKeyPadState *pxa27x_keypad_init(hwaddr base,
    119                 qemu_irq irq);
    120 void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map,
    121                 int size);
    122 
    123 /* pxa2xx.c */
    124 typedef struct PXA2xxI2CState PXA2xxI2CState;
    125 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
    126                 qemu_irq irq, uint32_t page_size);
    127 i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
    128 
    129 typedef struct PXA2xxI2SState PXA2xxI2SState;
    130 typedef struct PXA2xxFIrState PXA2xxFIrState;
    131 
    132 typedef struct {
    133     CPUOldState *env;
    134     qemu_irq *pic;
    135     qemu_irq reset;
    136     PXA2xxDMAState *dma;
    137     PXA2xxGPIOInfo *gpio;
    138     PXA2xxLCDState *lcd;
    139     SSIBus **ssp;
    140     PXA2xxI2CState *i2c[2];
    141     PXA2xxMMCIState *mmc;
    142     PXA2xxPCMCIAState *pcmcia[2];
    143     PXA2xxI2SState *i2s;
    144     PXA2xxFIrState *fir;
    145     PXA2xxKeyPadState *kp;
    146 
    147     /* Power management */
    148     hwaddr pm_base;
    149     uint32_t pm_regs[0x40];
    150 
    151     /* Clock management */
    152     hwaddr cm_base;
    153     uint32_t cm_regs[4];
    154     uint32_t clkcfg;
    155 
    156     /* Memory management */
    157     hwaddr mm_base;
    158     uint32_t mm_regs[0x1a];
    159 
    160     /* Performance monitoring */
    161     uint32_t pmnc;
    162 
    163     /* Real-Time clock */
    164     hwaddr rtc_base;
    165     uint32_t rttr;
    166     uint32_t rtsr;
    167     uint32_t rtar;
    168     uint32_t rdar1;
    169     uint32_t rdar2;
    170     uint32_t ryar1;
    171     uint32_t ryar2;
    172     uint32_t swar1;
    173     uint32_t swar2;
    174     uint32_t piar;
    175     uint32_t last_rcnr;
    176     uint32_t last_rdcr;
    177     uint32_t last_rycr;
    178     uint32_t last_swcr;
    179     uint32_t last_rtcpicr;
    180     int64_t last_hz;
    181     int64_t last_sw;
    182     int64_t last_pi;
    183     QEMUTimer *rtc_hz;
    184     QEMUTimer *rtc_rdal1;
    185     QEMUTimer *rtc_rdal2;
    186     QEMUTimer *rtc_swal1;
    187     QEMUTimer *rtc_swal2;
    188     QEMUTimer *rtc_pi;
    189 } PXA2xxState;
    190 
    191 struct PXA2xxI2SState {
    192     qemu_irq irq;
    193     PXA2xxDMAState *dma;
    194     void (*data_req)(void *, int, int);
    195 
    196     uint32_t control[2];
    197     uint32_t status;
    198     uint32_t mask;
    199     uint32_t clk;
    200 
    201     int enable;
    202     int rx_len;
    203     int tx_len;
    204     void (*codec_out)(void *, uint32_t);
    205     uint32_t (*codec_in)(void *);
    206     void *opaque;
    207 
    208     int fifo_len;
    209     uint32_t fifo[16];
    210 };
    211 
    212 # define PA_FMT			"0x%08lx"
    213 # define REG_FMT		"0x" TARGET_FMT_plx
    214 
    215 PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision);
    216 PXA2xxState *pxa255_init(unsigned int sdram_size);
    217 
    218 /* usb-ohci.c */
    219 void usb_ohci_init_pxa(hwaddr base, int num_ports, int devfn,
    220                        qemu_irq irq);
    221 
    222 #endif	/* PXA_H */
    223