| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.h | 27 const NVPTXRegisterInfo RegInfo;
32 const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
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| NVPTXPrologEpilogPass.cpp | 112 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
212 (RegInfo->needsStackRealignment(Fn) && MFI->getObjectIndexEnd() != 0))
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| NVPTXInstrInfo.cpp | 33 : NVPTXGenInstrInfo(), RegInfo(STI) {}
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| /external/llvm/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 56 const Thumb1RegisterInfo *RegInfo =
75 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
78 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
92 const Thumb1RegisterInfo *RegInfo =
104 unsigned FramePtr = RegInfo->getFrameRegister(MF);
105 unsigned BasePtr = RegInfo->getBaseRegister();
118 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
129 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
260 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
281 if (RegInfo->needsStackRealignment(MF)
[all...] |
| ARMFrameLowering.cpp | 50 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
60 RegInfo->needsStackRealignment(MF) ||
166 const ARMBaseRegisterInfo *RegInfo =
178 unsigned FramePtr = RegInfo->getFrameRegister(MF);
516 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) {
550 if (RegInfo->hasBasePointer(MF)) {
553 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
558 RegInfo->getBaseRegister())
577 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
587 unsigned FramePtr = RegInfo->getFrameRegister(MF)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 131 const MipsRegisterInfo &RegInfo =
134 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
138 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
151 const MipsRegisterInfo &RegInfo =
154 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
160 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
174 const MipsRegisterInfo &RegInfo =
177 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
181 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
182 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi)
[all...] |
| MipsSERegisterInfo.cpp | 171 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
172 unsigned Reg = RegInfo.createVirtualRegister(RC);
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| Mips16ISelDAGToDAG.cpp | 73 MachineRegisterInfo &RegInfo = MF.getRegInfo();
80 V0 = RegInfo.createVirtualRegister(RC);
81 V1 = RegInfo.createVirtualRegister(RC);
82 V2 = RegInfo.createVirtualRegister(RC);
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| MipsISelLowering.cpp | [all...] |
| MipsSEISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 49 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
52 RegInfo->needsStackRealignment(MF) ||
442 const X86RegisterInfo *RegInfo =
462 unsigned SlotSize = RegInfo->getSlotSize();
463 unsigned FramePtr = RegInfo->getFrameRegister(MF);
464 unsigned StackPtr = RegInfo->getStackRegister();
465 unsigned BasePtr = RegInfo->getBaseRegister();
492 !RegInfo->needsStackRealignment(MF) &&
538 if (RegInfo->needsStackRealignment(MF)) {
567 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(FramePtr, true)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 89 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
90 assert(!RegInfo->needsStackRealignment(MF) &&
207 const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
299 if (RegInfo->hasBasePointer(MF))
305 unsigned FramePtr = RegInfo->getFrameRegister(MF);
375 unsigned Reg = RegInfo->getDwarfRegNum(FramePtr, true);
382 unsigned LR = RegInfo->getDwarfRegNum(AArch64::LR, true);
439 const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
496 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
550 const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>
[all...] |
| AArch64CleanupLocalDynamicTLSPass.cpp | 120 MachineRegisterInfo &RegInfo = MF->getRegInfo();
121 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass);
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| /external/llvm/lib/CodeGen/ |
| MachineFunction.cpp | 59 RegInfo = new (Allocator) MachineRegisterInfo(TM);
61 RegInfo = nullptr;
96 if (RegInfo) {
97 RegInfo->~MachineRegisterInfo();
98 Allocator.Deallocate(RegInfo);
336 if (RegInfo) {
337 OS << (RegInfo->isSSA() ? "SSA" : "Post SSA");
338 if (!RegInfo->tracksLiveness())
355 if (RegInfo && !RegInfo->livein_empty())
[all...] |
| MachineInstr.cpp | 131 MachineRegisterInfo *RegInfo = nullptr;
135 RegInfo = &MF->getRegInfo();
139 if (RegInfo && WasReg)
140 RegInfo->removeRegOperandFromUseList(this);
162 if (RegInfo)
163 RegInfo->addRegOperandToUseList(this);
[all...] |
| PrologEpilogInserter.cpp | 242 const TargetRegisterInfo *RegInfo = F.getTarget().getRegisterInfo();
247 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&F);
271 if (!TFI->assignCalleeSavedSpillSlots(F, RegInfo, CSI)) {
286 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
289 if (RegInfo->hasReservedSpillSlot(F, Reg, FrameIdx)) {
518 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
521 RegInfo->useFPForScavengingIndex(Fn) &&
522 !RegInfo->needsStackRealignment(Fn));
650 (RegInfo->needsStackRealignment(Fn) && MFI->getObjectIndexEnd() != 0))
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 359 const MCRegisterInfo *RegInfo;
383 const MCRegisterInfo *RegInfo,
388 Op->RegIdx.RegInfo = RegInfo;
402 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
410 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
420 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID)
428 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
436 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
444 return RegIdx.RegInfo->getRegClass(Mips::FGRH32RegClassID
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineFunction.h | 82 // RegInfo - Information about each register in use in the function.
83 MachineRegisterInfo *RegInfo;
167 MachineRegisterInfo &getRegInfo() { return *RegInfo; }
168 const MachineRegisterInfo &getRegInfo() const { return *RegInfo; }
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| FunctionLoweringInfo.h | 57 MachineRegisterInfo *RegInfo;
|
| MachineInstr.h | [all...] |
| SelectionDAGISel.h | 47 MachineRegisterInfo *RegInfo;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 374 const PPCRegisterInfo *RegInfo =
391 !RegInfo->hasBasePointer(MF)) { // No special alignment.
461 const PPCRegisterInfo *RegInfo =
463 bool HasBP = RegInfo->hasBasePointer(MF);
501 const PPCRegisterInfo *RegInfo =
546 bool HasBP = RegInfo->hasBasePointer(MF);
816 const PPCRegisterInfo *RegInfo =
849 bool HasBP = RegInfo->hasBasePointer(MF);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 803 const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo();
805 RegInfo->getFrameRegister(MF), MVT::i32);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 64 RegInfo = &MF->getRegInfo();
248 return RegInfo->
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 435 MachineRegisterInfo &RegInfo = MF->getRegInfo();
439 GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);
|
