/external/llvm/include/llvm/CodeGen/ |
MachineInstrBuilder.h | 29 namespace RegState { 69 flags & RegState::Define, 70 flags & RegState::Implicit, 71 flags & RegState::Kill, 72 flags & RegState::Dead, 73 flags & RegState::Undef, 74 flags & RegState::EarlyClobber, 76 flags & RegState::Debug, 77 flags & RegState::InternalRead)); 242 .addReg(DestReg, RegState::Define) [all...] |
/external/llvm/lib/Target/XCore/ |
XCoreRegisterInfo.cpp | 108 .addReg(ScratchOffset, RegState::Kill) 115 .addReg(ScratchOffset, RegState::Kill) 121 .addReg(ScratchOffset, RegState::Kill); 184 .addReg(ScratchBase, RegState::Kill) 185 .addReg(ScratchOffset, RegState::Kill) 191 .addReg(ScratchBase, RegState::Kill) 192 .addReg(ScratchOffset, RegState::Kill) 197 .addReg(ScratchBase, RegState::Kill) 198 .addReg(ScratchOffset, RegState::Kill);
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
SIInstrInfo.cpp | 56 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
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R600InstrInfo.cpp | 59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define) 63 .addReg(DestReg, RegState::Define | RegState::Implicit); 82 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); 281 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); 291 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); 463 MachineInstrBuilder(MI).addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
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R600ISelLowering.cpp | 173 .addReg(t0, RegState::Implicit) 174 .addReg(t1, RegState::Implicit); 195 .addReg(t0, RegState::Implicit) 196 .addReg(t1, RegState::Implicit); 215 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); 229 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
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/external/mesa3d/src/gallium/drivers/radeon/ |
SIInstrInfo.cpp | 56 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
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R600InstrInfo.cpp | 59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define) 63 .addReg(DestReg, RegState::Define | RegState::Implicit); 82 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); 281 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); 291 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); 463 MachineInstrBuilder(MI).addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
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R600ISelLowering.cpp | 173 .addReg(t0, RegState::Implicit) 174 .addReg(t1, RegState::Implicit); 195 .addReg(t0, RegState::Implicit) 196 .addReg(t1, RegState::Implicit); 215 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); 229 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
FastISel.cpp | [all...] |
InstrEmitter.cpp | 240 MIB.addReg(VRBase, RegState::Define); 253 MIB.addReg(VRBase, RegState::Define); 265 MIB.addReg(VRBase, RegState::Define); 696 MIB.addReg(0U, RegState::Debug); 791 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine | 792 RegState::EarlyClobber); [all...] |
/external/llvm/lib/Target/ARM/ |
Thumb2InstrInfo.cpp | 199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); 200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); 205 MIB.addReg(DestReg, RegState::ImplicitDefine); 219 .addReg(BaseReg, RegState::Kill) 251 .addReg(BaseReg, RegState::Kill) 252 .addReg(DestReg, RegState::Kill) 257 .addReg(DestReg, RegState::Kill) 258 .addReg(BaseReg, RegState::Kill) 323 .addReg(BaseReg, RegState::Kill)
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Thumb1RegisterInfo.cpp | 121 .addReg(LdReg, RegState::Kill).setMIFlags(MIFlags); 133 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); 135 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); 243 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal)); 246 .addReg(BaseReg, RegState::Kill)) 291 .addReg(DestReg, RegState::Kill) 319 .addReg(DestReg, RegState::Kill)); 518 .addReg(ARM::R12, RegState::Define) 519 .addReg(Reg, RegState::Kill)); 548 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill)) [all...] |
ARMFrameLowering.cpp | 321 .addReg(ARM::R4, RegState::Implicit) 332 .addReg(ARM::R12, RegState::Kill) 333 .addReg(ARM::R4, RegState::Implicit) 340 .addReg(ARM::SP, RegState::Define) 341 .addReg(ARM::R4, RegState::Kill) 523 .addReg(ARM::SP, RegState::Kill) 533 .addReg(ARM::SP, RegState::Kill)); 536 .addReg(ARM::R4, RegState::Kill) 539 .addReg(ARM::R4, RegState::Kill)); 689 addReg(JumpTarget.getReg(), RegState::Kill) [all...] |
ARMExpandPseudoInsts.cpp | 397 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 399 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 401 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 403 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 434 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 487 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg. 530 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 532 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 534 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 536 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)) [all...] |
ARMBaseInstrInfo.cpp | [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCRegisterInfo.cpp | 340 .addReg(NegSizeReg1, RegState::Kill); 345 .addReg(Reg, RegState::Kill) 365 .addReg(NegSizeReg1, RegState::Kill); 370 .addReg(Reg, RegState::Kill) 420 .addReg(Reg1, RegState::Kill) 427 .addReg(Reg, RegState::Kill), 465 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 470 .addReg(Reg, RegState::Kill); 538 .addReg(Reg1, RegState::Kill) 543 .addReg(Reg, RegState::Kill) [all...] |
PPCFrameLowering.cpp | 308 .addReg(SrcReg, RegState::Kill) 317 .addReg(SrcReg, RegState::Kill) 326 .addReg(SrcReg, RegState::Kill) 330 .addReg(DstReg, RegState::Kill) 629 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); 686 .addReg(ScratchReg, RegState::Kill) 692 .addReg(TempReg, RegState::Kill) 695 .addReg(ScratchReg, RegState::Kill) 696 .addReg(TempReg, RegState::Kill); 699 .addReg(SPReg, RegState::Kill [all...] |
/external/llvm/lib/Target/Mips/ |
Mips16InstrInfo.cpp | 90 MIB.addReg(DestReg, RegState::Define); 252 addSaveRestoreRegs(MIB, CSI, RegState::Define); 254 MIB.addReg(Mips::S2, RegState::Define); 281 MIB2.addReg(Mips::SP, RegState::Kill); 284 MIB3.addReg(Reg2, RegState::Kill); 287 MIB4.addReg(Reg1, RegState::Kill); 408 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill) 413 .addReg(Reg, RegState::Kill);
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MipsSEInstrInfo.cpp | 111 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); 133 .addReg(DestReg, RegState::ImplicitDefine); 173 MIB.addReg(DestReg, RegState::Define); 372 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill); 411 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill) 483 LoInst.addReg(DstLo, RegState::Define); 484 HiInst.addReg(DstHi, RegState::Define); 509 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); 525 // FIXME: The .addReg(SrcReg, RegState::Implicit) is a white lie used to 537 SrcReg, RegState::Implicit) [all...] |
MipsSERegisterInfo.cpp | 194 .addReg(Reg, RegState::Kill);
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/external/llvm/lib/Target/AArch64/ |
AArch64ExpandPseudoInsts.cpp | 109 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 187 RegState::Define | getDeadRegState(DstIsDead && CountThree)) 211 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 361 RegState::Define | getDeadRegState(DstIsDead && SingleMovk)) 377 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 526 .addReg(DstReg, RegState::Define | 551 RegState::Define | 644 .addReg(SrcH, RegState::Undef)
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/external/llvm/lib/Target/R600/ |
SILowerControlFlow.cpp | 414 .addReg(AMDGPU::M0, RegState::Implicit) 415 .addReg(Vec, RegState::Implicit); 434 .addReg(SubReg + Off, RegState::Define) 436 .addReg(AMDGPU::M0, RegState::Implicit) 437 .addReg(Dst, RegState::Implicit);
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/external/llvm/lib/Target/SystemZ/ |
SystemZElimCompare.cpp | 207 .addReg(SystemZ::CC, RegState::ImplicitDefine); 221 .addReg(SystemZ::CC, RegState::ImplicitDefine); 411 .addReg(SystemZ::CC, RegState::ImplicitDefine);
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SystemZRegisterInfo.cpp | 123 .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
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/external/llvm/lib/Target/MSP430/ |
MSP430FrameLowering.cpp | 67 .addReg(MSP430::FPW, RegState::Kill); 200 .addReg(Reg, RegState::Kill);
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