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    Searched refs:ResultReg (Results 1 - 7 of 7) sorted by null

  /external/llvm/lib/CodeGen/SelectionDAG/
FastISel.cpp 391 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
394 if (ResultReg == 0) return false;
397 UpdateValueMap(I, ResultReg);
427 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
429 if (ResultReg == 0) return false;
432 UpdateValueMap(I, ResultReg);
438 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
440 if (ResultReg != 0) {
442 UpdateValueMap(I, ResultReg);
455 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT()
    [all...]
  /external/llvm/lib/Target/Mips/
MipsFastISel.cpp 72 bool EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
155 bool MipsFastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
163 ResultReg = createResultReg(&Mips::GPR32RegClass);
168 ResultReg = createResultReg(&Mips::GPR32RegClass);
173 ResultReg = createResultReg(&Mips::GPR32RegClass);
178 ResultReg = createResultReg(&Mips::FGR32RegClass);
183 ResultReg = createResultReg(&Mips::AFGR64RegClass);
190 EmitInstLoad(Opc, ResultReg, Addr.Base.Reg, Addr.Offset);
258 unsigned ResultReg;
259 if (!EmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment())
    [all...]
  /external/llvm/lib/Target/AArch64/
AArch64FastISel.cpp 125 bool EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
186 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
188 ResultReg)
192 return ResultReg;
217 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
218 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
220 return ResultReg;
235 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
236 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
239 return ResultReg;
    [all...]
  /external/llvm/lib/Target/X86/
X86FastISel.cpp 84 unsigned &ResultReg);
93 unsigned &ResultReg);
365 MachineMemOperand *MMO, unsigned &ResultReg) {
412 ResultReg = createResultReg(RC);
414 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
534 unsigned &ResultReg) {
540 ResultReg = RR;
    [all...]
  /external/llvm/lib/Target/PowerPC/
PPCFastISel.cpp 145 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
407 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
409 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
410 Addr.Base.Reg = ResultReg;
427 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
433 // If ResultReg is given, it determines the register class of the load.
441 (ResultReg ? MRI.getRegClass(ResultReg) :
486 if (ResultReg == 0)
487 ResultReg = createResultReg(UseRC)
    [all...]
  /external/llvm/lib/Target/ARM/
ARMFastISel.cpp 173 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
289 unsigned ResultReg = createResultReg(RC);
297 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
302 TII.get(TargetOpcode::COPY), ResultReg)
305 return ResultReg;
312 unsigned ResultReg = createResultReg(RC);
322 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
330 TII.get(TargetOpcode::COPY), ResultReg)
333 return ResultReg;
341 unsigned ResultReg = createResultReg(RC)
    [all...]
  /external/llvm/lib/Target/R600/
SIInstrInfo.cpp     [all...]

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