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  /system/core/libpixelflinger/codeflinger/
MIPSAssembler.h 272 void ADDU(int Rd, int Rs, int Rt);
273 void ADDIU(int Rt, int Rs, int16_t imm);
274 void SUBU(int Rd, int Rs, int Rt);
275 void SUBIU(int Rt, int Rs, int16_t imm);
277 void MUL(int Rd, int Rs, int Rt);
278 void MULT(int Rs, int Rt); // dest is hi,lo
279 void MULTU(int Rs, int Rt); // dest is hi,lo
280 void MADD(int Rs, int Rt); // hi,lo = hi,lo + Rs * Rt
281 void MADDU(int Rs, int Rt); // hi,lo = hi,lo + Rs * R
    [all...]
MIPSAssembler.cpp     [all...]
Arm64Assembler.cpp 1003 uint32_t size, uint32_t Rt,
1009 dataTransferOpName[op], Rt, Rn, Rm);
1010 return(dataTransferOpCode[op] | (Rm << 16) | (Rn << 5) | Rt);
1015 dataTransferOpName[op], Rt, Rn, Rm);
1016 return(dataTransferOpCode[op] | (0x1<<30) | (Rm<<16) | (Rn<<5)|Rt);
1020 uint32_t ArmToArm64Assembler::A64_STR_IMM_PreIndex(uint32_t Rt,
1024 LOG_INSTR("STR W%d, [SP, #%d]!\n", Rt, simm);
1026 LOG_INSTR("STR W%d, [X%d, #%d]!\n", Rt, Rn, simm);
1029 return (0xB8 << 24) | (imm9 << 12) | (0x3 << 10) | (Rn << 5) | Rt;
1032 uint32_t ArmToArm64Assembler::A64_LDR_IMM_PostIndex(uint32_t Rt,
    [all...]
Arm64Assembler.h 198 uint32_t size, uint32_t Rt,
201 uint32_t A64_STR_IMM_PreIndex(uint32_t Rt, uint32_t Rn, int32_t simm);
202 uint32_t A64_LDR_IMM_PostIndex(uint32_t Rt,uint32_t Rn, int32_t simm);
  /external/eigen/Eigen/src/Geometry/
Umeyama.h 135 TransformationMatrixType Rt = TransformationMatrixType::Identity(m+1,m+1);
146 Rt.block(0,0,m,m).noalias() = svd.matrixU()*svd.matrixV().transpose();
149 Rt.block(0,0,m,m).noalias() = svd.matrixU() * S.asDiagonal() * svd.matrixV().transpose();
153 Rt.block(0,0,m,m).noalias() = svd.matrixU() * S.asDiagonal() * svd.matrixV().transpose();
162 Rt.col(m).head(m) = dst_mean;
163 Rt.col(m).head(m).noalias() -= c*Rt.topLeftCorner(m,m)*src_mean;
164 Rt.block(0,0,m,m) *= c;
168 Rt.col(m).head(m) = dst_mean;
169 Rt.col(m).head(m).noalias() -= Rt.topLeftCorner(m,m)*src_mean
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  /frameworks/rs/java/tests/ImageProcessing2/src/com/android/rs/image/
vibrance.rs 27 static float Rt = 0.f;
43 Rt = Rf * MS;
51 float Rc = R * (Rt + S) + G * Gt + B * Bt;
52 float Gc = R * Rt + G * (Gt + S) + B * Bt;
53 float Bc = R * Rt + G * Gt + B * (Bt + S);
66 Rt = Rf * MS;
  /frameworks/rs/java/tests/ImageProcessing/src/com/android/rs/image/
vibrance.rs 35 float Rt = Rf * MS;
44 float Rc = R * (Rt + S) + G * Gt + B * Bt;
45 float Gc = R * Rt + G * (Gt + S) + B * Bt;
46 float Bc = R * Rt + G * Gt + B * (Bt + S);
  /frameworks/rs/java/tests/ImageProcessing_jb/src/com/android/rs/image/
vibrance.rs 35 float Rt = Rf * MS;
44 float Rc = R * (Rt + S) + G * Gt + B * Bt;
45 float Gc = R * Rt + G * (Gt + S) + B * Bt;
46 float Bc = R * Rt + G * Gt + B * (Bt + S);
  /packages/apps/Gallery2/jni/filters/
saturated.c 30 float Rt = Rf * MS;
44 float Rc = R * (Rt + S) + G * Gt + B * Bt;
45 float Gc = R * Rt + G * (Gt + S) + B * Bt;
46 float Bc = R * Rt + G * Gt + B * (Bt + S);
vibrance.c 32 float Rt = Rf * MS;
45 Rt = Rf * MS;
53 float Rc = R * (Rt + S) + G * Gt + B * Bt;
54 float Gc = R * Rt + G * (Gt + S) + B * Bt;
55 float Bc = R * Rt + G * Gt + B * (Bt + S);
  /packages/apps/Gallery2/src/com/android/gallery3d/filtershow/filters/
saturation.rs 70 float Rt = Rf * MS;
76 rsMatrixSet(&colorMatrix_max, 0, 0, b * (Rt + S));
79 rsMatrixSet(&colorMatrix_max, 0, 1, b * Rt);
82 rsMatrixSet(&colorMatrix_max, 0, 2, b * Rt);
88 Rt = Rf * MS;
93 rsMatrixSet(&colorMatrix_min, 0, 0, b * (Rt + S));
96 rsMatrixSet(&colorMatrix_min, 0, 1, b * Rt);
99 rsMatrixSet(&colorMatrix_min, 0, 2, b * Rt);
vignette.rs 48 float Rt = Rf * MS;
56 rsMatrixSet(&colorMatrix, 0, 0, b * (Rt + S));
59 rsMatrixSet(&colorMatrix, 0, 1, b * Rt);
62 rsMatrixSet(&colorMatrix, 0, 2, b * Rt);
grad.rs 72 float Rt = Rf * MS;
80 rsMatrixSet(&grads[i].colorMatrix, 0, 0, b * (Rt + S));
83 rsMatrixSet(&grads[i].colorMatrix, 0, 1, b * Rt);
86 rsMatrixSet(&grads[i].colorMatrix, 0, 2, b * Rt);
  /art/disassembler/
disassembler_arm.cc 510 ArmRegister Rt(instr, 12);
523 args << Rt << "," << Rd << ", [" << Rn;
538 args << Rd << ", " << Rt << ", [" << Rn << ", #" << (imm8 << 2) << "]";
539 if (Rd.r == 13 || Rd.r == 15 || Rt.r == 13 || Rt.r == 15 || Rn.r == 15 ||
540 Rd.r == Rn.r || Rd.r == Rt.r) {
551 args << Rd << ", " << Rt << ", [" << Rn << "]";
552 if (Rd.r == 13 || Rd.r == 15 || Rt.r == 13 || Rt.r == 15 || Rn.r == 15 ||
553 Rd.r == Rn.r || Rd.r == Rt.r || (instr & 0xf00) != 0xf00)
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  /external/llvm/lib/Target/Mips/Disassembler/
MipsDisassembler.cpp 453 // BOVC if rs >= rt
454 // BEQZALC if rs == 0 && rt != 0
455 // BEQC if rs < rt && rs != 0
458 InsnType Rt = fieldFromInstruction(insn, 16, 5);
462 if (Rs >= Rt) {
465 } else if (Rs != 0 && Rs < Rt) {
476 Rt)));
492 // BNVC if rs >= rt
493 // BNEZALC if rs == 0 && rt != 0
494 // BNEC if rs < rt && rs !=
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  /external/llvm/lib/Target/AArch64/Disassembler/
AArch64Disassembler.cpp     [all...]
  /external/llvm/lib/Target/ARM/Disassembler/
ARMDisassembler.cpp     [all...]
  /external/vixl/src/a64/
assembler-a64.cc 479 void Assembler::cbz(const Register& rt,
481 Emit(SF(rt) | CBZ | ImmCmpBranch(imm19) | Rt(rt));
485 void Assembler::cbz(const Register& rt,
487 cbz(rt, UpdateAndGetInstructionOffsetTo(label));
491 void Assembler::cbnz(const Register& rt,
493 Emit(SF(rt) | CBNZ | ImmCmpBranch(imm19) | Rt(rt));
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simulator-a64.cc 559 bool bit_zero = ((xreg(instr->Rt()) >> bit_pos) & 1) == 0;
573 unsigned rt = instr->Rt();
576 case CBZ_w: take_branch = (wreg(rt) == 0); break;
577 case CBZ_x: take_branch = (xreg(rt) == 0); break;
578 case CBNZ_w: take_branch = (wreg(rt) != 0); break;
579 case CBNZ_x: take_branch = (xreg(rt) != 0); break;
776 unsigned srcdst = instr->Rt();
841 unsigned rt = instr->Rt(); local
906 unsigned rt = instr->Rt(); local
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  /external/chromium_org/v8/src/arm64/
assembler-arm64.cc 463 Assembler::Rt(xzr));
499 instr->preceding()->Rt() == xzr.code());
894 bool result = instr->IsLdrLiteralX() && (instr->Rt() == xzr.code());
1011 void Assembler::cbz(const Register& rt,
1014 Emit(SF(rt) | CBZ | ImmCmpBranch(imm19) | Rt(rt));
1018 void Assembler::cbz(const Register& rt,
1021 cbz(rt, LinkAndGetInstructionOffsetTo(label));
1025 void Assembler::cbnz(const Register& rt,
    [all...]
simulator-arm64.cc 1349 unsigned rt = instr->Rt(); local
1669 unsigned rt = instr->Rt(); local
1799 unsigned rt = instr->Rt(); local
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  /external/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp     [all...]
  /external/lldb/source/Plugins/Instruction/ARM/
EmulateInstructionARM.cpp 367 uint32_t Rt; // the source register
386 Rt = Bits32(opcode, 15, 12);
388 if (BadReg(Rt))
390 registers = (1u << Rt);
399 Rt = Bits32(opcode, 15, 12);
401 if (Rt == dwarf_sp)
403 registers = (1u << Rt);
490 uint32_t Rt; // the destination register
512 Rt = Bits32(opcode, 15, 12);
514 if (Rt == 13
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  /external/llvm/lib/Target/AArch64/AsmParser/
AArch64AsmParser.cpp     [all...]
  /external/llvm/test/MC/AArch64/
arm64-diags.s 155 ; Load pair instructions where Rt==Rt2 and writeback load/store instructions
156 ; where Rt==Rn or Rt2==Rn are unpredicatable.
185 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt

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