| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 28 case ISD::SRA: return ARM_AM::asr;
|
| /external/pcre/dist/sljit/ |
| sljitNativeSPARC_32.c | 60 return push_inst(compiler, SRA | D(dst) | S1(dst) | IMM(24), DR(dst));
71 return push_inst(compiler, (op == SLJIT_MOV_SH ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst));
112 FAIL_IF(push_inst(compiler, SRA | D(TMP_REG1) | S1(dst) | IMM(31), DR(TMP_REG1)));
134 FAIL_IF(push_inst(compiler, SRA | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst)));
|
| sljitNativeMIPS_32.c | 91 return push_inst(compiler, SRA | T(dst) | D(dst) | SH_IMM(24), DR(dst));
109 return push_inst(compiler, SRA | T(dst) | D(dst) | SH_IMM(16), DR(dst));
312 FAIL_IF(push_inst(compiler, SRA | T(dst) | DA(UGREATER_FLAG) | SH_IMM(31), UGREATER_FLAG));
336 EMIT_SHIFT(SRA, SRAV);
|
| sljitNativeMIPS_64.c | 407 FAIL_IF(push_inst(compiler, SELECT_OP(DSRA32, SRA) | T(dst) | DA(UGREATER_FLAG) | SH_IMM(31), UGREATER_FLAG));
431 EMIT_SHIFT(DSRA, DSRA32, SRA, DSRAV, SRAV);
|
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 210 { ISD::SRA, MVT::v4i32, 1 },
213 { ISD::SRA, MVT::v8i32, 1 },
225 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized.
226 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized.
227 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized.
269 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
270 { ISD::SRA, MVT::v8i16, 1 }, // psraw.
271 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
325 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized.
326 { ISD::SRA, MVT::v8i16, 8*10 }, // Scalarized
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | 399 case ASR: mMips->SRA(tmpReg, amode.reg, amode.value); break;
510 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break;
542 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break;
[all...] |
| /external/chromium_org/v8/src/mips/ |
| constants-mips.cc | 226 case SRA:
|
| constants-mips.h | 375 SRA = ((0 << 3) + 3),
|
| /external/chromium_org/v8/src/mips64/ |
| constants-mips64.cc | 230 case SRA:
|
| constants-mips64.h | 352 SRA = ((0 << 3) + 3),
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 311 SHL, SRA, SRL, ROTL, ROTR,
375 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
|
| MSP430ISelLowering.cpp | 92 setOperationAction(ISD::SRA, MVT::i8, Custom);
95 setOperationAction(ISD::SRA, MVT::i16, Custom);
189 case ISD::SRA: return LowerShifts(Op, DAG);
752 case ISD::SRA:
753 return DAG.getNode(MSP430ISD::SRA, dl,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 76 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
600 return DAG.getNode(ISD::SRA, SDLoc(N), Res.getValueType(), Res, Amt);
[all...] |
| LegalizeVectorOps.cpp | 18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
254 case ISD::SRA:
550 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
723 // Make sure that the SRA and SHL instructions are available.
724 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
737 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
781 return DAG.getNode(ISD::SRA, DL, VT,
[all...] |
| DAGCombiner.cpp | [all...] |
| FastISel.cpp | 412 // Transform "sdiv exact X, 8" -> "sra X, 3".
417 ISDOpcode = ISD::SRA;
[all...] |
| SelectionDAGBuilder.h | 714 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
|
| SelectionDAGDumper.cpp | 178 case ISD::SRA: return "sra";
|
| /external/valgrind/main/none/tests/mips64/ |
| shift_instructions.c | 10 SRA, SRAV, SRL, SRLV
177 case SRA:
178 TEST2("sra $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
179 TEST2("sra $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
180 TEST2("sra $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
181 TEST2("sra $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
|
| /external/linux-tools-perf/perf-3.12.0/arch/mips/lib/ |
| memcpy.S | 112 #define SRA dsra
149 #define SRA sra
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 442 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift);
512 jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT));
|
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | [all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 442 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift);
512 jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT));
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 95 SRL, SRA, SHL,
|
