| /external/llvm/lib/Transforms/Utils/ |
| IntegerDivision.cpp | 30 /// should be pointing where the caller wants code generated, e.g. at the srem
57 // ; %srem = sub i32 %xored, %dividend_sgn
66 Value *SRem = Builder.CreateSub(Xored, DividendSign);
71 return SRem;
377 assert((Rem->getOpcode() == Instruction::SRem ||
393 if (Rem->getOpcode() == Instruction::SRem) {
486 assert((Rem->getOpcode() == Instruction::SRem ||
512 if (Rem->getOpcode() == Instruction::SRem) {
536 assert((Rem->getOpcode() == Instruction::SRem ||
562 if (Rem->getOpcode() == Instruction::SRem) {
[all...] |
| BypassSlowDivision.cpp | 234 bool UseRemOp = Opcode == Instruction::SRem || Opcode == Instruction::URem;
236 Opcode == Instruction::SRem;
|
| SimplifyIndVar.cpp | 252 bool IsSigned = Rem->getOpcode() == Instruction::SRem;
|
| /external/llvm/unittests/Transforms/Utils/ |
| IntegerDivision.cpp | 83 TEST(IntegerDivision, SRem) {
102 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SRem);
223 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SRem);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreLowerThreadLocal.cpp | 95 case Instruction::SRem:
|
| /external/llvm/lib/Transforms/ObjCARC/ |
| ObjCARCUtil.cpp | 220 case Instruction::SRem: case Instruction::URem: case Instruction::FRem:
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCompares.cpp | [all...] |
| InstCombineVectorOps.cpp | 619 case Instruction::SRem:
682 case Instruction::SRem:
781 case Instruction::SRem:
[all...] |
| InstCombineSimplifyDemanded.cpp | 716 case Instruction::SRem:
724 if (DemandedMask.ult(RA)) // srem won't affect demanded bits
733 // The low bits of LHS are unchanged by the srem.
[all...] |
| /external/lldb/source/Expression/ |
| IRInterpreter.cpp | 517 case Instruction::SRem:
622 case Instruction::SRem:
689 case Instruction::SRem:
[all...] |
| /external/llvm/lib/Analysis/ |
| CostModel.cpp | 405 case Instruction::SRem:
|
| ValueTracking.cpp | 534 case Instruction::SRem:
541 // The low bits of the first operand are unchanged by the srem.
[all...] |
| InstructionSimplify.cpp | [all...] |
| /external/llvm/lib/IR/ |
| Instruction.cpp | 212 case SRem: return "srem";
|
| ConstantFold.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 210 case Instruction::SRem:
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCCTRLoops.cpp | 371 J->getOpcode() == Instruction::SRem)) {
|
| /external/llvm/include/llvm/IR/ |
| PatternMatch.h | 454 inline BinaryOp_match<LHS, RHS, Instruction::SRem>
456 return BinaryOp_match<LHS, RHS, Instruction::SRem>(L, R);
[all...] |
| /external/llvm/lib/Target/CppBackend/ |
| CPPBackend.cpp | 876 case Instruction::SRem: Out << "getSRem("; break;
[all...] |
| /external/llvm/lib/ExecutionEngine/ |
| ExecutionEngine.cpp | 768 case Instruction::SRem:
786 case Instruction::SRem:GV.IntVal = LHS.IntVal.srem(RHS.IntVal); break;
[all...] |
| /external/llvm/lib/AsmParser/ |
| LLLexer.cpp | 703 INSTKEYWORD(urem, URem); INSTKEYWORD(srem, SRem); INSTKEYWORD(frem, FRem);
|
| /external/llvm/tools/llvm-stress/ |
| llvm-stress.cpp | 347 case 5:{Op = (isFloat?Instruction::FRem : Instruction::SRem); break; }
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinter.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXAsmPrinter.cpp | 234 case Instruction::SRem:
252 case Instruction::SRem:
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | [all...] |
