| /external/llvm/lib/Target/ARM/ |
| ARMRegisterInfo.h | 26 ARMRegisterInfo(const ARMSubtarget &STI);
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| ARMInstrInfo.h | 26 explicit ARMInstrInfo(const ARMSubtarget &STI);
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| Thumb2RegisterInfo.h | 26 Thumb2RegisterInfo(const ARMSubtarget &STI);
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.h | 40 bool isMicroMips(const MCSubtargetInfo &STI) const;
50 void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI,
55 const MCSubtargetInfo &STI) const override;
61 const MCSubtargetInfo &STI) const;
68 const MCSubtargetInfo &STI) const;
75 const MCSubtargetInfo &STI) const;
82 const MCSubtargetInfo &STI) const;
89 const MCSubtargetInfo &STI) const;
96 const MCSubtargetInfo &STI) const;
103 const MCSubtargetInfo &STI) const
[all...] |
| MipsELFStreamer.cpp | 15 const MCSubtargetInfo &STI, bool RelaxAll,
17 return new MipsELFStreamer(Context, MAB, OS, Emitter, STI);
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| MipsELFStreamer.h | 31 MCCodeEmitter *Emitter, const MCSubtargetInfo &STI)
39 const MCSubtargetInfo &STI, bool RelaxAll,
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| MipsMCCodeEmitter.cpp | 38 const MCSubtargetInfo &STI,
45 const MCSubtargetInfo &STI,
116 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
117 return STI.getFeatureBits() & Mips::FeatureMicroMips;
125 const MCSubtargetInfo &STI,
131 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
132 EmitInstruction(Val >> 16, 2, STI, OS);
133 EmitInstruction(Val, 2, STI, OS);
147 const MCSubtargetInfo &STI) const
170 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
[all...] |
| MipsNaClELFStreamer.cpp | 40 MCCodeEmitter *Emitter, const MCSubtargetInfo &STI)
41 : MipsELFStreamer(Context, TAB, OS, Emitter, STI), PendingCall(false) {}
94 const MCSubtargetInfo &STI) {
100 MipsELFStreamer::EmitInstruction(MaskInst, STI);
105 void sandboxIndirectJump(const MCInst &MI, const MCSubtargetInfo &STI) {
109 emitMask(AddrReg, IndirectBranchMaskReg, STI);
110 MipsELFStreamer::EmitInstruction(MI, STI);
117 const MCSubtargetInfo &STI, bool MaskBefore,
123 emitMask(BaseReg, LoadStoreStackMaskReg, STI);
125 MipsELFStreamer::EmitInstruction(MI, STI);
[all...] |
| MipsMCNaCl.h | 28 const MCSubtargetInfo &STI,
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| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| AMDGPUMCCodeEmitter.h | 33 const MCSubtargetInfo &STI) const;
37 const MCSubtargetInfo &STI) const {
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| AMDGPUMCTargetDesc.cpp | 70 const MCSubtargetInfo &STI) {
76 const MCSubtargetInfo &STI,
78 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
79 return createSIMCCodeEmitter(MCII, MRI, STI, Ctx);
81 return createR600MCCodeEmitter(MCII, MRI, STI);
89 const MCSubtargetInfo &STI,
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| AMDGPUMCTargetDesc.h | 36 const MCSubtargetInfo &STI);
40 const MCSubtargetInfo &STI,
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| /external/llvm/include/llvm/MC/ |
| MCDisassembler.h | 58 MCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
59 : Ctx(Ctx), STI(STI), Symbolizer(), CommentStream(nullptr) {}
90 const MCSubtargetInfo &STI;
108 const MCSubtargetInfo& getSubtargetInfo() const { return STI; }
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| MCCodeEmitter.h | 40 const MCSubtargetInfo &STI) const = 0;
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| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZMCCodeEmitter.cpp | 40 const MCSubtargetInfo &STI) const override;
46 const MCSubtargetInfo &STI) const;
52 const MCSubtargetInfo &STI) const;
60 const MCSubtargetInfo &STI) const;
63 const MCSubtargetInfo &STI) const;
66 const MCSubtargetInfo &STI) const;
69 const MCSubtargetInfo &STI) const;
72 const MCSubtargetInfo &STI) const;
84 const MCSubtargetInfo &STI) const {
89 const MCSubtargetInfo &STI) const
[all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCCodeEmitter.cpp | 41 AArch64MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
51 const MCSubtargetInfo &STI) const;
57 const MCSubtargetInfo &STI) const;
65 const MCSubtargetInfo &STI) const;
71 const MCSubtargetInfo &STI) const;
77 const MCSubtargetInfo &STI) const;
83 const MCSubtargetInfo &STI) const;
89 const MCSubtargetInfo &STI) const;
96 const MCSubtargetInfo &STI) const;
102 const MCSubtargetInfo &STI) const
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
| AMDGPUMCTargetDesc.h | 32 const MCSubtargetInfo &STI,
36 const MCSubtargetInfo &STI,
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.h | 26 AArch64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
27 : MCDisassembler(STI, Ctx) {}
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| /external/llvm/lib/Target/Mips/ |
| MipsFrameLowering.h | 25 const MipsSubtarget &STI;
28 explicit MipsFrameLowering(const MipsSubtarget &sti, unsigned Alignment)
29 : TargetFrameLowering(StackGrowsDown, Alignment, 0, Alignment), STI(sti) {}
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| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| AMDGPUMCTargetDesc.h | 32 const MCSubtargetInfo &STI,
36 const MCSubtargetInfo &STI,
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 53 bool isThumb(const MCSubtargetInfo &STI) const {
54 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
56 bool isThumb2(const MCSubtargetInfo &STI) const {
57 return isThumb(STI) && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
59 bool isTargetMachO(const MCSubtargetInfo &STI) const {
60 Triple TT(STI.getTargetTriple());
70 const MCSubtargetInfo &STI) const;
76 const MCSubtargetInfo &STI) const;
83 const MCSubtargetInfo &STI) const
[all...] |
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 50 const MCSubtargetInfo &STI) const;
53 const MCSubtargetInfo &STI) const;
56 const MCSubtargetInfo &STI) const;
59 const MCSubtargetInfo &STI) const;
62 const MCSubtargetInfo &STI) const;
65 const MCSubtargetInfo &STI) const;
68 const MCSubtargetInfo &STI) const;
71 const MCSubtargetInfo &STI) const;
74 const MCSubtargetInfo &STI) const;
77 const MCSubtargetInfo &STI) const
[all...] |
| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| SparcMCCodeEmitter.cpp | 45 const MCSubtargetInfo &STI) const override;
51 const MCSubtargetInfo &STI) const;
57 const MCSubtargetInfo &STI) const;
61 const MCSubtargetInfo &STI) const;
64 const MCSubtargetInfo &STI) const;
67 const MCSubtargetInfo &STI) const;
70 const MCSubtargetInfo &STI) const;
77 const MCSubtargetInfo &STI,
85 const MCSubtargetInfo &STI) const {
86 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmInstrumentation.h | 31 const MCContext &Ctx, const MCSubtargetInfo &STI);
47 const MCContext &Ctx, const MCSubtargetInfo &STI);
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| /external/llvm/include/llvm/CodeGen/ |
| TargetSchedule.h | 37 const TargetSubtargetInfo *STI;
44 TargetSchedModel(): STI(nullptr), TII(nullptr) {}
51 void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,
115 return STI->getWriteProcResBegin(SC);
118 return STI->getWriteProcResEnd(SC);
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