| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.cpp | 28 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
30 if (SUnits[su].getInstr()->isCall())
31 LastSequentialCall = &(SUnits[su]);
33 else if (SUnits[su].getInstr()->isCompare() && LastSequentialCall)
34 SUnits[su].addPred(SDep(LastSequentialCall, SDep::Barrier));
38 /// Check if scheduling of this SU is possible
43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) {
44 if (!SU || !SU->getInstr()
[all...] |
| HexagonMachineScheduler.h | 87 bool isResourceAvailable(SUnit *SU);
88 bool reserveResources(SUnit *SU);
115 SUnit *SU;
123 SchedCandidate(): SU(nullptr), SCost(0) {}
176 bool checkHazard(SUnit *SU);
178 void releaseNode(SUnit *SU, unsigned ReadyCycle);
182 void bumpNode(SUnit *SU);
186 void removeReady(SUnit *SU);
214 virtual void schedNode(SUnit *SU, bool IsTopNode) override;
216 virtual void releaseTopNode(SUnit *SU) override
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ResourcePriorityQueue.h | 88 void addNode(const SUnit *SU) override {
92 void updateNode(const SUnit *SU) override {}
108 /// Single cost function reflecting benefit of scheduling SU
110 signed SUSchedulingCost (SUnit *SU);
114 void initNumRegDefsLeft(SUnit *SU);
115 void updateNumRegDefsLeft(SUnit *SU);
116 signed regPressureDelta(SUnit *SU, bool RawPressure = false);
117 signed rawRegPressureDelta (SUnit *SU, unsigned RCId);
125 void remove(SUnit *SU) override;
131 bool isResourceAvailable(SUnit *SU);
[all...] |
| ScheduleDAGInstrs.h | 36 SUnit *SU;
38 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
48 SUnit *SU;
52 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
174 const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
175 if (!SU->SchedClass && SchedModel.hasInstrSchedModel()
[all...] |
| LatencyPriorityQueue.h | 57 void addNode(const SUnit *SU) override {
61 void updateNode(const SUnit *SU) override {
84 void remove(SUnit *SU) override;
95 void AdjustPriorityOfUnscheduledPreds(SUnit *SU);
96 SUnit *getSingleUnscheduledPred(SUnit *SU);
|
| MachineScheduler.h | 200 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
204 virtual void releaseTopNode(SUnit *SU) = 0;
207 virtual void releaseBottomNode(SUnit *SU) = 0;
281 /// \brief Add a DAG edge to the given SU with the given predecessor
325 void updateQueues(SUnit *SU, bool IsTopNode);
339 void releaseSucc(SUnit *SU, SDep *SuccEdge);
340 void releaseSuccessors(SUnit *SU);
341 void releasePred(SUnit *SU, SDep *PredEdge);
342 void releasePredecessors(SUnit *SU);
358 // Map each SU to its summary of pressure changes. This array is updated fo
[all...] |
| ScheduleDFS.h | 146 unsigned getNumInstrs(const SUnit *SU) const {
147 return DFSNodeData[SU->NodeNum].InstrCount;
159 ILPValue getILP(const SUnit *SU) const {
160 return ILPValue(DFSNodeData[SU->NodeNum].InstrCount, 1 + SU->getDepth());
170 unsigned getSubtreeID(const SUnit *SU) const {
173 assert(SU->NodeNum < DFSNodeData.size() && "New Node");
174 return DFSNodeData[SU->NodeNum].SubtreeID;
|
| ScoreboardHazardRecognizer.h | 115 // Stalls provides an cycle offset at which SU will be scheduled. It will be
117 HazardType getHazardType(SUnit *SU, int Stalls) override;
119 void EmitInstruction(SUnit *SU) override;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ResourcePriorityQueue.cpp | 72 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) {
74 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
109 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU,
112 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
147 static unsigned numberCtrlDepsInSU(SUnit *SU) {
149 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
157 static unsigned numberCtrlPredInSU(SUnit *SU) {
650 SUnit *su = q.pop(); local
[all...] |
| ScheduleDAGVLIW.cpp | 88 void releaseSucc(SUnit *SU, const SDep &D);
89 void releaseSuccessors(SUnit *SU);
90 void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
117 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) {
132 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency());
141 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) {
143 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
148 releaseSucc(SU, *I);
155 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigned CurCycle)
[all...] |
| ScheduleDAGRRList.cpp | 186 /// IsReachable - Checks if SU is reachable from TargetSU.
187 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) {
188 return Topo.IsReachable(SU, TargetSU);
191 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
193 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
194 return Topo.WillCreateCycle(SU, TargetSU);
197 /// AddPred - adds a predecessor edge to SUnit SU.
200 void AddPred(SUnit *SU, const SDep &D) {
201 Topo.AddPred(SU, D.getSUnit());
202 SU->addPred(D)
[all...] |
| ScheduleDAGSDNodes.cpp | 79 SUnit *SU = &SUnits.back();
84 SU->SchedulingPref = Sched::None;
86 SU->SchedulingPref = TLI.getSchedulingPreference(N);
87 return SU;
91 SUnit *SU = newSUnit(Old->getNode());
92 SU->OrigNode = Old->OrigNode;
93 SU->Latency = Old->Latency;
94 SU->isVRegCycle = Old->isVRegCycle;
95 SU->isCall = Old->isCall;
96 SU->isCallOp = Old->isCallOp
[all...] |
| ScheduleDAGSDNodes.h | 92 void InitVRegCycleFlag(SUnit *SU);
96 void InitNumRegDefsLeft(SUnit *SU);
100 virtual void computeLatency(SUnit *SU);
120 void dumpNode(const SUnit *SU) const override;
124 std::string getGraphNodeLabel(const SUnit *SU) const override;
140 RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD);
180 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
|
| ScheduleDAGFast.cpp | 86 /// AddPred - adds a predecessor edge to SUnit SU.
88 void AddPred(SUnit *SU, const SDep &D) {
89 SU->addPred(D);
92 /// RemovePred - removes a predecessor edge from SUnit SU.
94 void RemovePred(SUnit *SU, const SDep &D) {
95 SU->removePred(D);
99 void ReleasePred(SUnit *SU, SDep *PredEdge);
100 void ReleasePredecessors(SUnit *SU, unsigned CurCycle);
127 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.h | 31 bool isLoadAfterStore(SUnit *SU);
32 bool isBCTRAfterSet(SUnit *SU);
40 HazardType getHazardType(SUnit *SU, int Stalls) override;
41 bool ShouldPreferAnother(SUnit* SU) override;
42 unsigned PreEmitNoops(SUnit *SU) override;
43 void EmitInstruction(SUnit *SU) override;
79 virtual HazardType getHazardType(SUnit *SU, int Stalls) override;
80 virtual void EmitInstruction(SUnit *SU) override;
|
| PPCHazardRecognizers.cpp | 26 bool PPCDispatchGroupSBHazardRecognizer::isLoadAfterStore(SUnit *SU) {
28 if (isBCTRAfterSet(SU))
31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
38 // SU is a load; for any predecessors in this dispatch group, that are stores,
40 for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) {
41 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit());
45 if (!SU->Preds[i].isNormalMemory() && !SU->Preds[i].isBarrier())
49 if (SU->Preds[i].getSUnit() == CurGroup[j])
56 bool PPCDispatchGroupSBHazardRecognizer::isBCTRAfterSet(SUnit *SU) {
[all...] |
| /external/llvm/lib/CodeGen/ |
| LatencyPriorityQueue.cpp | 55 /// of SU, return it, otherwise return null.
56 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) {
58 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
73 void LatencyPriorityQueue::push(SUnit *SU) {
77 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
79 if (getSingleUnscheduledPred(I->getSUnit()) == SU)
82 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking;
84 Queue.push_back(SU);
148 SUnit *su = q.pop(); local
[all...] |
| ScheduleDAGInstrs.cpp | 207 /// the exit SU to the register defs and use list. This is because we want to
250 /// MO is an operand of SU's instruction that defines a physical register. Add
251 /// data dependencies from SU to any uses of the physical register.
252 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
253 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
264 SUnit *UseSU = I->SU;
265 if (UseSU == SU)
274 Dep = SDep(SU, SDep::Artificial);
278 SU->hasPhysRegDefs = true;
279 Dep = SDep(SU, SDep::Data, *Alias)
[all...] |
| MachineScheduler.cpp | 520 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
537 // SU->TopReadyCycle was set to CurrCycle when it was scheduled. However,
539 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency())
540 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency();
547 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
548 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
549 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
551 releaseSucc(SU, &*I);
559 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge)
[all...] |
| ScheduleDAG.cpp | 184 SUnit *SU = WorkList.pop_back_val();
185 SU->isDepthCurrent = false;
186 for (SUnit::const_succ_iterator I = SU->Succs.begin(),
187 E = SU->Succs.end(); I != E; ++I) {
200 SUnit *SU = WorkList.pop_back_val();
201 SU->isHeightCurrent = false;
202 for (SUnit::const_pred_iterator I = SU->Preds.begin(),
203 E = SU->Preds.end(); I != E; ++I) {
318 dbgs() << "SU(" << NodeNum << "): ";
347 dbgs() << "SU(" << I->getSUnit()->NodeNum << ")"
[all...] |
| ScoreboardHazardRecognizer.cpp | 119 ScoreboardHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
129 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
166 DEBUG(dbgs() << "SU(" << SU->NodeNum << "): ");
167 DEBUG(DAG->dumpNode(SU));
179 void ScoreboardHazardRecognizer::EmitInstruction(SUnit *SU) {
185 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
|
| /external/llvm/lib/Target/R600/ |
| R600MachineScheduler.cpp | 60 SUnit *SU = nullptr;
96 if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) ||
99 SU = pickAlu();
100 if (!SU && !PhysicalRegCopy.empty()) {
101 SU = PhysicalRegCopy.front();
104 if (SU) {
111 if (!SU) {
113 SU = pickOther(IDFetch);
114 if (SU)
119 if (!SU) {
[all...] |
| R600MachineScheduler.h | 78 void schedNode(SUnit *SU, bool IsTopNode) override;
79 void releaseTopNode(SUnit *SU) override;
80 void releaseBottomNode(SUnit *SU) override;
86 int getInstKind(SUnit *SU);
88 AluKind getAluKind(SUnit *SU) const;
|
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.h | 40 HazardType getHazardType(SUnit *SU, int Stalls) override;
42 void EmitInstruction(SUnit *SU) override;
|
| ARMHazardRecognizer.cpp | 35 ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
38 MachineInstr *MI = SU->getInstr();
76 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
85 void ARMHazardRecognizer::EmitInstruction(SUnit *SU) {
86 MachineInstr *MI = SU->getInstr();
92 ScoreboardHazardRecognizer::EmitInstruction(SU);
|
