| /art/compiler/dex/quick/ |
| gen_loadstore.cc | 69 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), temp_reg, k32, kNotVolatile);
308 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg, k64, kNotVolatile);
372 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg, k64, kNotVolatile);
|
| mir_to_lir.h | [all...] |
| ralloc_util.cc | 763 StoreBaseDisp(TargetPtrReg(kSp), VRegOffset(v_reg), reg, k64, kNotVolatile);
771 StoreBaseDisp(TargetPtrReg(kSp), VRegOffset(v_reg), reg, k64, kNotVolatile);
783 StoreBaseDisp(TargetPtrReg(kSp), VRegOffset(v_reg), reg, kWord, kNotVolatile);
[all...] |
| gen_invoke.cc | [all...] |
| gen_common.cc | 604 StoreBaseDisp(r_base, field_info.FieldOffset().Int32Value(), rl_src.reg, store_size,
793 null_ck_insn = StoreBaseDisp(rl_obj.reg, field_offset, rl_src.reg, store_size,
[all...] |
| mir_to_lir.cc | 294 StoreBaseDisp(reg_obj, data.field_offset, reg_src, size, data.is_volatile ? kVolatile :
[all...] |
| /art/compiler/dex/quick/arm64/ |
| target_arm64.cc | [all...] |
| codegen_arm64.h | 85 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,
|
| utility_arm64.cc | [all...] |
| int_arm64.cc | 701 StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size, kNotVolatile);
[all...] |
| /art/compiler/dex/quick/x86/ |
| call_x86.cc | 294 setup_method_address_[1] = StoreBaseDisp(rs_rX86_SP, displacement, method_start,
|
| fp_x86.cc | 148 StoreBaseDisp(rs_rX86_SP, src_v_reg_offset, rl_src.reg, k64, kNotVolatile);
367 StoreBaseDisp(rs_rX86_SP, src1_v_reg_offset, rl_src1.reg, is_double ? k64 : k32,
378 StoreBaseDisp(rs_rX86_SP, src2_v_reg_offset, rl_src2.reg, is_double ? k64 : k32,
|
| target_x86.cc | 701 StoreBaseDisp(rs_rX86_SP, offset, cu_->target64 ? RegStorage::Solo64(reg) : RegStorage::Solo32(reg),
733 StoreBaseDisp(rs_rX86_SP, offset, RegStorage::FloatSolo64(reg),
[all...] |
| codegen_x86.h | 78 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
[all...] |
| utility_x86.cc | 870 LIR* X86Mir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,
876 // StoreBaseDisp() will emit correct insn for atomic store on x8
[all...] |
| int_x86.cc | 901 StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size, kNotVolatile);
[all...] |
| /art/compiler/dex/quick/arm/ |
| codegen_arm.h | 41 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
|
| int_arm.cc | 784 StoreBaseDisp(rl_address.reg, 0, rl_value.reg.GetLow(), k32, kNotVolatile);
785 StoreBaseDisp(rl_address.reg, 4, rl_value.reg.GetHigh(), k32, kNotVolatile);
790 StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size, kNotVolatile);
[all...] |
| utility_arm.cc | [all...] |
| /art/compiler/dex/quick/mips/ |
| codegen_mips.h | 41 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
|
| int_mips.cc | 323 StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size, kNotVolatile);
613 StoreBaseDisp(reg_ptr, 0, rl_src.reg, size, kNotVolatile);
|
| utility_mips.cc | 655 LIR* MipsMir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
|
