| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCInst.cpp | 33 const uint64_t F = MCID->TSFlags;
52 const uint64_t F = MCID->TSFlags;
58 const uint64_t F = MCID->TSFlags;
64 const uint64_t F = MCID->TSFlags;
70 const uint64_t F = MCID->TSFlags;
118 const uint64_t F = MCID->TSFlags;
124 const uint64_t F = MCID->TSFlags;
130 const uint64_t F = MCID->TSFlags;
136 const uint64_t F = MCID->TSFlags;
142 const uint64_t F = MCID->TSFlags;
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 148 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
156 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
163 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
187 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) {
188 assert((TSFlags & X86II::EncodingMask) >> X86II::EncodingShift == X86II::EVEX &&
191 unsigned CD8E = (TSFlags >> X86II::EVEX_CD8EShift) & X86II::EVEX_CD8EMask;
192 unsigned CD8V = (TSFlags >> X86II::EVEX_CD8VShift) & X86II::EVEX_CD8VMask;
205 bool EVEX_b = (TSFlags >> X86II::VEXShift) & X86II::EVEX_B;
207 unsigned EVEX_LL = ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) ? 1 : 0;
208 EVEX_LL += ((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2) ? 2 : 0
[all...] |
| X86BaseInfo.h | 550 inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
551 return TSFlags >> X86II::OpcodeShift;
554 inline bool hasImm(uint64_t TSFlags) {
555 return (TSFlags & X86II::ImmMask) != 0;
558 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
560 inline unsigned getSizeOfImm(uint64_t TSFlags) {
561 switch (TSFlags & X86II::ImmMask) {
575 /// TSFlags indicates that it is pc relative.
576 inline unsigned isImmPCRel(uint64_t TSFlags) {
577 switch (TSFlags & X86II::ImmMask)
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 70 // Look for the appropriate part of TSFlags
73 unsigned TSFlags =
74 (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift;
75 isMove = (TSFlags == 1);
115 unsigned TSFlags =
116 (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift;
117 isLoad = (TSFlags == 1);
126 unsigned TSFlags =
127 (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift;
128 isStore = (TSFlags == 1)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86CodeEmitter.cpp | 66 void emitOpcodePrefix(uint64_t TSFlags, int MemOperand,
70 void emitVEXOpcodePrefix(uint64_t TSFlags, int MemOperand,
74 void emitSegmentOverridePrefix(uint64_t TSFlags,
168 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
170 if (Desc.TSFlags & X86II::REX_W)
189 switch (Desc.TSFlags & X86II::FormMask) {
655 void Emitter<CodeEmitter>::emitOpcodePrefix(uint64_t TSFlags,
660 if (((TSFlags & X86II::OpSizeMask) >> X86II::OpSizeShift) == X86II::OpSize16)
663 switch (Desc->TSFlags & X86II::OpPrefixMask) {
682 switch (Desc->TSFlags & X86II::OpMapMask)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
57 (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) {
|
| ARMCodeEmitter.cpp | 455 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
535 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
[all...] |
| ARMBaseRegisterInfo.cpp | 446 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
636 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
752 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
753 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
|
| MLxExpansionPass.cpp | 188 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
352 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
|
| /external/llvm/lib/Target/R600/ |
| R600Defines.h | 62 #define IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST)
63 #define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
|
| SIInsertWaits.cpp | 125 uint64_t TSFlags = TII->get(MI.getOpcode()).TSFlags;
128 Result.Named.VM = !!(TSFlags & SIInstrFlags::VM_CNT);
131 Result.Named.EXP = !!(TSFlags & SIInstrFlags::EXP_CNT &&
135 if (TSFlags & SIInstrFlags::LGKM_CNT) {
|
| AMDGPUInstrInfo.cpp | 270 return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE;
274 return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD;
|
| R600OptimizeVectorRegisters.cpp | 133 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
249 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
330 if (TII->get(MI->getOpcode()).TSFlags & R600_InstFlag::TEX_INST) {
|
| R600InstrInfo.cpp | 41 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
45 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
138 unsigned TargetFlags = get(Opcode).TSFlags;
144 unsigned TargetFlags = get(Opcode).TSFlags;
152 unsigned TargetFlags = get(Opcode).TSFlags;
204 return (get(Opcode).TSFlags & R600_InstFlag::IS_EXPORT);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 287 uint64_t TSFlags = MCID.TSFlags;
289 isFirst = TSFlags & PPCII::PPC970_First;
290 isSingle = TSFlags & PPCII::PPC970_Single;
291 isCracked = TSFlags & PPCII::PPC970_Cracked;
292 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
|
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 136 ((Desc.TSFlags & R600_InstFlag::OP1) ||
137 Desc.TSFlags & R600_InstFlag::OP2)) {
175 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 46 uint64_t TSFlags = Desc.TSFlags;
48 if (TSFlags & X86II::LOCK)
|
| X86IntelInstPrinter.cpp | 38 uint64_t TSFlags = Desc.TSFlags;
40 if (TSFlags & X86II::LOCK)
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 590 const uint64_t F = MID.TSFlags;
611 const uint64_t F = MI->getDesc().TSFlags;
757 const uint64_t F = MI->getDesc().TSFlags;
763 const uint64_t F = get(Opcode).TSFlags;
983 const uint64_t F = MI->getDesc().TSFlags;
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 40 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
45 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
485 return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
490 unsigned FlagIndex = GET_FLAG_OPERAND_IDX(get(MI->getOpcode()).TSFlags);
|
| /external/llvm/lib/Target/Mips/ |
| MipsCodeEmitter.cpp | 175 uint64_t TSFlags = MI.getDesc().TSFlags;
176 uint64_t Form = TSFlags & MipsII::FormMask;
347 if (((MI->getDesc().TSFlags & MipsII::FormMask) == MipsII::Pseudo) &&
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 40 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
45 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
485 return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
490 unsigned FlagIndex = GET_FLAG_OPERAND_IDX(get(MI->getOpcode()).TSFlags);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 235 unsigned MIFlags = Desc.TSFlags;
241 unsigned CompareFlags = Compare->getDesc().TSFlags;
257 unsigned Flags = MI->getDesc().TSFlags;
|
| SystemZRegisterInfo.cpp | 104 if (MI->getDesc().TSFlags & SystemZII::HasIndex
|
| SystemZInstrInfo.cpp | 196 if ((MCID.TSFlags & Flag) &&
488 bool IsLogical = (Compare->getDesc().TSFlags & SystemZII::IsLogical) != 0;
625 return ((MCID.TSFlags & Flag) &&
847 uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
855 if (MemDesc.TSFlags & SystemZII::HasIndex)
[all...] |
