| /external/llvm/utils/TableGen/ |
| AsmWriterInst.cpp | 97 CGI.TheDef->getName() + "'!");
136 + CGI.TheDef->getName() + "'");
143 + CGI.TheDef->getName() + "'");
151 PrintFatalError("Bad operand modifier name in '"+ CGI.TheDef->getName() + "'");
156 + CGI.TheDef->getName() + "'");
160 PrintFatalError("Stray '$' in '" + CGI.TheDef->getName() +
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| CodeGenIntrinsics.h | 27 Record *TheDef; // The actual record defining this intrinsic.
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| InstrInfoEmitter.cpp | 209 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
221 OperandMap[OpList].push_back(Namespace + "::" + Inst->TheDef->getName());
362 Record *Inst = II->TheDef;
390 InstrNames.add(Inst->TheDef->getName());
408 OS << InstrNames.get(Inst->TheDef->getName()) << "U, ";
476 << Inst.TheDef->getValueAsInt("Size") << ",\t0";
509 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
517 PrintFatalError("Invalid TSFlags bit in " + Inst.TheDef->getName());
524 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
530 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs")
[all...] |
| CodeGenSchedule.h | 40 /// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or
41 /// may not be empty. TheDef is null for inferred sequences, and Sequence must
49 Record *TheDef;
59 : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false),
62 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) {
77 : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false),
83 assert((!HasVariants || TheDef) && "Variant write needs record def");
88 return TheDef || !Sequence.empty();
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| AsmMatcherEmitter.cpp | 394 /// TheDef - This is the definition of the instruction or InstAlias that this
396 Record *const TheDef;
437 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI),
442 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias),
565 Record *TheDef;
570 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
574 return "Feature_" + TheDef->getName();
579 TheDef->dump()
[all...] |
| AsmWriterEmitter.cpp | 111 << FirstInst.CGI->TheDef->getName() << ":\n";
114 << SimilarInsts[i].CGI->TheDef->getName() << ":\n";
125 FirstInst.CGI->TheDef->getName(),
131 AWI.CGI->TheDef->getName(),
175 InstrsForCase[idx] += Inst->CGI->TheDef->getName();
182 InstrsForCase.push_back(Inst->CGI->TheDef->getName());
405 << NumberedInstructions->at(i)->TheDef->getName() << "\n";
419 << NumberedInstructions->at(i)->TheDef->getName() << "\n";
535 AsmName = Reg.TheDef->getValueAsString("AsmName");
541 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices")
[all...] |
| CodeGenSchedule.cpp | 80 if (R.match((*I)->TheDef->getName()))
81 Elts.insert((*I)->TheDef);
219 Record *SchedDef = (*I)->TheDef;
298 findRWs(WI->TheDef->getValueAsListOfDefs("Writes"), WI->Sequence,
351 if (I->TheDef == Def)
359 Record *ReadDef = SchedReads[i].TheDef;
414 SchedRW.TheDef ? SchedRW.TheDef->getValueAsInt("Repeat") : 1;
440 PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
443 AliasDef = AliasRW.TheDef;
[all...] |
| CodeGenInstruction.h | 128 Record *TheDef; // The actual record containing this OperandList.
208 Record *TheDef; // The actual record defining this instruction.
288 Record *TheDef; // The actual record defining this InstAlias.
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| SubtargetEmitter.cpp | 676 if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes"))
677 return SchedWrite.TheDef;
684 if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) {
685 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
690 PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
693 AliasDef = AliasRW.TheDef;
705 || SchedWrite.TheDef == (*WRI)->getValueAsDef("WriteType")) {
719 + SchedWrite.TheDef->getName());
729 if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance"))
730 return SchedRead.TheDef;
[all...] |
| CodeGenInstruction.cpp | 28 CGIOperandList::CGIOperandList(Record *R) : TheDef(R) {
136 PrintFatalError("'" + TheDef->getName() +
156 PrintFatalError(TheDef->getName() + ": Illegal operand name: '" + Op + "'");
166 PrintFatalError(TheDef->getName() + ": illegal empty suboperand name in '" +Op +"'");
176 PrintFatalError(TheDef->getName() + ": Illegal to refer to"
186 PrintFatalError(TheDef->getName() + ": unknown suboperand name in '" + Op + "'");
194 PrintFatalError(TheDef->getName() + ": unknown suboperand name in '" + Op + "'");
293 : TheDef(R), Operands(R), InferredFrom(nullptr) {
558 : TheDef(R) {
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| CodeGenRegisters.h | 37 Record *const TheDef;
112 Record *TheDef;
125 // Extract more information from TheDef. This is used to build an object
251 Record *TheDef;
286 Record *getDef() const { return TheDef; }
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| CodeGenRegisters.cpp | 34 : TheDef(R), EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) {
44 : TheDef(nullptr), Name(N), Namespace(Nspace), Size(-1), Offset(-1),
57 if (!TheDef)
60 std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf");
63 PrintFatalError(TheDef->getLoc(),
69 PrintFatalError(TheDef->getLoc(), "Ambiguous ComposedOf entries");
73 TheDef->getValueAsListOfDefs("CoveringSubRegIndices");
76 PrintFatalError(TheDef->getLoc(),
107 : TheDef(R),
118 std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices")
[all...] |
| RegisterInfoEmitter.cpp | 76 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
324 Record *Reg = Regs[i]->TheDef;
342 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
391 Record *Reg = Regs[i]->TheDef;
447 Record *Reg = Regs[i]->TheDef;
455 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
839 OS << " { " << getQualifiedName(Roots.front()->TheDef);
841 OS << ", " << getQualifiedName(Roots[r]->TheDef);
[all...] |
| FixedLenDecoderEmitter.cpp | 374 BitsInit &Bits = getBitsField(*AllInstructions[Opcode]->TheDef, "Inst");
382 AllInstructions[Opcode]->TheDef->getValueAsBitsInit("SoftFail");
394 return AllInstructions[Opcode]->TheDef->getName();
830 << NumberedInstructions->at(Opc)->TheDef->getName() << "\n";
[all...] |
| CodeGenDAGPatterns.h | 751 if (Intrinsics[i].TheDef == R) return Intrinsics[i];
753 if (TgtIntrinsics[i].TheDef == R) return TgtIntrinsics[i];
767 if (Intrinsics[i].TheDef == R) return i;
769 if (TgtIntrinsics[i].TheDef == R) return i + Intrinsics.size();
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| PseudoLoweringEmitter.cpp | 212 << Source.TheDef->getName() << ": {\n"
216 << Dest.TheDef->getName() << ");\n";
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| CodeGenTarget.cpp | 327 return Rec1->TheDef->getName() < Rec2->TheDef->getName();
445 TheDef = R;
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| CodeEmitterGen.cpp | 260 Record *R = CGI->TheDef;
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| CodeGenMapTable.cpp | 375 Record *CurInstr = NumberedInstructions[i]->TheDef;
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| CodeGenDAGPatterns.cpp | [all...] |
| DAGISelMatcherEmitter.cpp | 460 OS << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n";
465 OS << getQualifiedName(Reg->TheDef) << ",\n";
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| IntrinsicEmitter.cpp | 754 PrintFatalError("Intrinsic '" + Ints[i].TheDef->getName() +
810 PrintFatalError("Intrinsic '" + Intrinsic.TheDef->getName() + "': "
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| X86RecognizableInstr.cpp | 179 Rec = insn.TheDef;
252 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
[all...] |
| DAGISelMatcherGen.cpp | [all...] |
