HomeSort by relevance Sort by last modified time
    Searched refs:ValueVT (Results 1 - 4 of 4) sorted by null

  /external/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.cpp 95 MVT PartVT, EVT ValueVT, const Value *V);
99 /// larger then ValueVT then AssertOp can be used to specify whether the extra
100 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
104 unsigned NumParts, MVT PartVT, EVT ValueVT,
107 if (ValueVT.isVector())
109 PartVT, ValueVT, V);
117 if (ValueVT.isInteger()) {
119 unsigned ValueBits = ValueVT.getSizeInBits();
126 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
167 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &
    [all...]
LegalizeTypesGeneric.cpp 251 EVT ValueVT = LD->getValueType(0);
252 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT);
282 if (TLI.hasBigEndianPartOrdering(ValueVT))
466 EVT ValueVT = St->getValue().getValueType();
467 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT);
481 if (TLI.hasBigEndianPartOrdering(ValueVT))
FunctionLoweringInfo.cpp 267 EVT ValueVT = ValueVTs[Value];
268 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
270 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
  /external/llvm/lib/Target/R600/
R600ISelLowering.cpp     [all...]

Completed in 572 milliseconds