/external/llvm/lib/Target/R600/ |
SIFixSGPRCopies.cpp | 124 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) 143 const TargetRegisterClass *RC = MRI.getRegClass(Reg); 170 return TRI->getSubRegClass(MRI.getRegClass(Reg), SubReg); 184 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg); 189 MRI.getRegClass(SrcReg) == &AMDGPU::VReg_1RegClass) 192 SrcRC = TRI->getSubRegClass(MRI.getRegClass(SrcReg), SrcSubReg); 235 if (!TRI->isSGPRClass(MRI.getRegClass(Reg))) 242 if (TRI->hasVGPRs(MRI.getRegClass(Reg))) { 263 DstRC = MRI.getRegClass(MI.getOperand(0).getReg()); 264 Src0RC = MRI.getRegClass(MI.getOperand(1).getReg()) [all...] |
SILowerI1Copies.cpp | 112 MRI.getRegClass(MI.getOperand(0).getReg()); 114 MRI.getRegClass(MI.getOperand(1).getReg());
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SIFixSGPRLiveRanges.cpp | 95 const TargetRegisterClass *RC = MRI.getRegClass(Def.getReg());
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SIInstrInfo.cpp | 377 RI.isSGPRClass(MRI.getRegClass(MI->getOperand(1).getReg()))) 590 const TargetRegisterClass *RC = RI.getRegClass(RegClass); 740 return MRI.getRegClass(MI.getOperand(OpNo).getReg()); 743 return RI.getRegClass(RCID); 763 const TargetRegisterClass *RC = RI.getRegClass(RCID); 874 RI.isSGPRClass(MRI.getRegClass(Src0.getReg()))) { 880 RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) { 888 (Src1.isReg() && RI.isSGPRClass(MRI.getRegClass(Src1.getReg())))) { 909 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg()))) [all...] |
/external/llvm/lib/CodeGen/ |
AllocationOrder.cpp | 36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
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RegAllocBase.cpp | 105 << MRI->getRegClass(VirtReg->reg)->getName() 130 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
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TargetRegisterInfo.cpp | 97 const TargetRegisterClass *SubRC = getRegClass(Idx + Offset); 166 return TRI->getRegClass(I + countTrailingZeros(Common));
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PeepholeOptimizer.cpp | 279 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); 290 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; 377 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); 543 const TargetRegisterClass *DefRC = MRI->getRegClass(Def); 569 const TargetRegisterClass *SrcRC = MRI->getRegClass(Src); [all...] |
LiveRangeEdit.cpp | 35 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); 44 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); 415 << MRI.getRegClass(LI.reg)->getName() << '\n');
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MachineSink.cpp | 126 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg); 127 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); 512 if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg)))
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VirtRegMap.cpp | 105 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); 126 << MRI->getRegClass(Reg)->getName() << "\n"; 134 << "] " << MRI->getRegClass(Reg)->getName() << "\n";
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CalcSpillWeights.cpp | 64 const TargetRegisterClass *rc = mri.getRegClass(reg);
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OptimizePHIs.cpp | 170 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
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Spiller.cpp | 88 const TargetRegisterClass *trc = mri->getRegClass(li->reg);
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/external/llvm/lib/Target/R600/InstPrinter/ |
AMDGPUInstPrinter.cpp | 64 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) { 67 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) { 70 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) { 73 } else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) { 76 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) { 79 } else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) { 82 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) { 85 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) { 88 } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) { 91 } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(reg)) [all...] |
/external/llvm/lib/Target/ARM/ |
A15SDOptimizer.cpp | 140 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); 277 MRI->getRegClass(MI->getOperand(1).getReg()); 278 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { 537 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || 538 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { 554 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { 560 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && 664 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
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/external/llvm/lib/Target/AArch64/ |
AArch64AdvSIMDScalarPass.cpp | 105 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); 112 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && 114 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&
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AArch64ConditionalCompares.cpp | 596 MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF)); 605 TII->getRegClass(MCID, 1, TRI, *MF)); 652 TII->getRegClass(MCID, 0, TRI, *MF)); 655 TII->getRegClass(MCID, 1, TRI, *MF));
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/external/llvm/lib/CodeGen/SelectionDAG/ |
InstrEmitter.cpp | 136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); 161 DstRC = MRI->getRegClass(VRBase); 221 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); 250 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 331 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); 438 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); 495 TRC == MRI->getRegClass(SrcReg)) { 546 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) 587 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); 604 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx) [all...] |
/external/llvm/lib/Target/NVPTX/ |
NVPTXInstrInfo.cpp | 39 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); 40 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
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/external/llvm/lib/Target/Mips/AsmParser/ |
MipsAsmParser.cpp | 402 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 410 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 420 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID) 428 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID) 436 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID) 444 return RegIdx.RegInfo->getRegClass(Mips::FGRH32RegClassID) 452 return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID) 463 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 471 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 479 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index) [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
AMDGPUInstrInfo.cpp | 249 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg());
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/external/llvm/utils/TableGen/ |
CodeGenTarget.h | 125 return *getRegBank().getRegClass(R);
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/external/mesa3d/src/gallium/drivers/radeon/ |
AMDGPUInstrInfo.cpp | 249 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg());
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/external/llvm/lib/Target/AArch64/InstPrinter/ |
AArch64InstPrinter.cpp | [all...] |