1 //===-- llvm/CodeGen/Spiller.cpp - Spiller -------------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "Spiller.h" 11 #include "llvm/CodeGen/LiveIntervalAnalysis.h" 12 #include "llvm/CodeGen/LiveRangeEdit.h" 13 #include "llvm/CodeGen/LiveStackAnalysis.h" 14 #include "llvm/CodeGen/MachineFrameInfo.h" 15 #include "llvm/CodeGen/MachineFunction.h" 16 #include "llvm/CodeGen/MachineInstrBuilder.h" 17 #include "llvm/CodeGen/MachineLoopInfo.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 #include "llvm/CodeGen/VirtRegMap.h" 20 #include "llvm/Support/CommandLine.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/ErrorHandling.h" 23 #include "llvm/Support/raw_ostream.h" 24 #include "llvm/Target/TargetInstrInfo.h" 25 #include "llvm/Target/TargetMachine.h" 26 27 using namespace llvm; 28 29 #define DEBUG_TYPE "spiller" 30 31 namespace { 32 enum SpillerName { trivial, inline_ }; 33 } 34 35 static cl::opt<SpillerName> 36 spillerOpt("spiller", 37 cl::desc("Spiller to use: (default: standard)"), 38 cl::Prefix, 39 cl::values(clEnumVal(trivial, "trivial spiller"), 40 clEnumValN(inline_, "inline", "inline spiller"), 41 clEnumValEnd), 42 cl::init(trivial)); 43 44 // Spiller virtual destructor implementation. 45 Spiller::~Spiller() {} 46 47 namespace { 48 49 /// Utility class for spillers. 50 class SpillerBase : public Spiller { 51 protected: 52 MachineFunctionPass *pass; 53 MachineFunction *mf; 54 VirtRegMap *vrm; 55 LiveIntervals *lis; 56 MachineFrameInfo *mfi; 57 MachineRegisterInfo *mri; 58 const TargetInstrInfo *tii; 59 const TargetRegisterInfo *tri; 60 61 /// Construct a spiller base. 62 SpillerBase(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm) 63 : pass(&pass), mf(&mf), vrm(&vrm) 64 { 65 lis = &pass.getAnalysis<LiveIntervals>(); 66 mfi = mf.getFrameInfo(); 67 mri = &mf.getRegInfo(); 68 tii = mf.getTarget().getInstrInfo(); 69 tri = mf.getTarget().getRegisterInfo(); 70 } 71 72 /// Add spill ranges for every use/def of the live interval, inserting loads 73 /// immediately before each use, and stores after each def. No folding or 74 /// remat is attempted. 75 void trivialSpillEverywhere(LiveRangeEdit& LRE) { 76 LiveInterval* li = &LRE.getParent(); 77 78 DEBUG(dbgs() << "Spilling everywhere " << *li << "\n"); 79 80 assert(li->weight != llvm::huge_valf && 81 "Attempting to spill already spilled value."); 82 83 assert(!TargetRegisterInfo::isStackSlot(li->reg) && 84 "Trying to spill a stack slot."); 85 86 DEBUG(dbgs() << "Trivial spill everywhere of reg" << li->reg << "\n"); 87 88 const TargetRegisterClass *trc = mri->getRegClass(li->reg); 89 unsigned ss = vrm->assignVirt2StackSlot(li->reg); 90 91 // Iterate over reg uses/defs. 92 for (MachineRegisterInfo::reg_instr_iterator 93 regItr = mri->reg_instr_begin(li->reg); 94 regItr != mri->reg_instr_end();) { 95 96 // Grab the use/def instr. 97 MachineInstr *mi = &*regItr; 98 99 DEBUG(dbgs() << " Processing " << *mi); 100 101 // Step regItr to the next use/def instr. 102 ++regItr; 103 104 // Collect uses & defs for this instr. 105 SmallVector<unsigned, 2> indices; 106 bool hasUse = false; 107 bool hasDef = false; 108 for (unsigned i = 0; i != mi->getNumOperands(); ++i) { 109 MachineOperand &op = mi->getOperand(i); 110 if (!op.isReg() || op.getReg() != li->reg) 111 continue; 112 hasUse |= mi->getOperand(i).isUse(); 113 hasDef |= mi->getOperand(i).isDef(); 114 indices.push_back(i); 115 } 116 117 // Create a new virtual register for the load and/or store. 118 unsigned NewVReg = LRE.create(); 119 120 // Update the reg operands & kill flags. 121 for (unsigned i = 0; i < indices.size(); ++i) { 122 unsigned mopIdx = indices[i]; 123 MachineOperand &mop = mi->getOperand(mopIdx); 124 mop.setReg(NewVReg); 125 if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) { 126 mop.setIsKill(true); 127 } 128 } 129 assert(hasUse || hasDef); 130 131 // Insert reload if necessary. 132 MachineBasicBlock::iterator miItr(mi); 133 if (hasUse) { 134 MachineInstrSpan MIS(miItr); 135 136 tii->loadRegFromStackSlot(*mi->getParent(), miItr, NewVReg, ss, trc, 137 tri); 138 lis->InsertMachineInstrRangeInMaps(MIS.begin(), miItr); 139 } 140 141 // Insert store if necessary. 142 if (hasDef) { 143 MachineInstrSpan MIS(miItr); 144 145 tii->storeRegToStackSlot(*mi->getParent(), std::next(miItr), NewVReg, 146 true, ss, trc, tri); 147 lis->InsertMachineInstrRangeInMaps(std::next(miItr), MIS.end()); 148 } 149 } 150 } 151 }; 152 153 } // end anonymous namespace 154 155 namespace { 156 157 /// Spills any live range using the spill-everywhere method with no attempt at 158 /// folding. 159 class TrivialSpiller : public SpillerBase { 160 public: 161 162 TrivialSpiller(MachineFunctionPass &pass, MachineFunction &mf, 163 VirtRegMap &vrm) 164 : SpillerBase(pass, mf, vrm) {} 165 166 void spill(LiveRangeEdit &LRE) override { 167 // Ignore spillIs - we don't use it. 168 trivialSpillEverywhere(LRE); 169 } 170 }; 171 172 } // end anonymous namespace 173 174 void Spiller::anchor() { } 175 176 llvm::Spiller* llvm::createSpiller(MachineFunctionPass &pass, 177 MachineFunction &mf, 178 VirtRegMap &vrm) { 179 switch (spillerOpt) { 180 case trivial: return new TrivialSpiller(pass, mf, vrm); 181 case inline_: return createInlineSpiller(pass, mf, vrm); 182 } 183 llvm_unreachable("Invalid spiller optimization"); 184 } 185