/external/llvm/test/MC/Mips/ |
micromips-16-bit-instructions.s | 15 # CHECK-EL: jalr $9 # encoding: [0xc9,0x45] 22 # CHECK-EB: jalr $9 # encoding: [0x45,0xc9] 27 jalr $9
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mips-jump-instructions.s | 96 # CHECK32: jalr $6 # encoding: [0x09,0xf8,0xc0,0x00] 98 # CHECK32: jalr $25 # encoding: [0x09,0xf8,0x20,0x03] 100 # CHECK32: jalr $10, $11 # encoding: [0x09,0x50,0x60,0x01] 107 # CHECK32: jalr $25 # encoding: [0x09,0xf8,0x20,0x03] 109 # CHECK32: jalr $4, $25 # encoding: [0x09,0x20,0x20,0x03] 119 # CHECK64: jalr $6 # encoding: [0x09,0xf8,0xc0,0x00] 121 # CHECK64: jalr $25 # encoding: [0x09,0xf8,0x20,0x03] 123 # CHECK64: jalr $10, $11 # encoding: [0x09,0x50,0x60,0x01] 130 # CHECK64: jalr $25 # encoding: [0x09,0xf8,0x20,0x03] 132 # CHECK64: jalr $4, $25 # encoding: [0x09,0x20,0x20,0x03 [all...] |
micromips-jump-instructions.s | 16 # CHECK-EL: jalr $ra, $6 # encoding: [0xe6,0x03,0x3c,0x0f] 29 # CHECK-EB: jalr $ra, $6 # encoding: [0x03,0xe6,0x0f,0x3c] 38 jalr $ra, $6
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elf-tls.s | 37 jalr $25 69 jalr $25 101 jalr $25
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elf-N64.s | 42 jalr $25
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xgot.s | 48 jalr $25
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r-mips-got-disp.s | 36 jalr $25
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nacl-mask.s | 252 jalr $t9 284 # CHECK-NEXT: jalr $25 301 jalr $t9 318 # CHECK-NEXT: jalr
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/bionic/linker/arch/mips/ |
begin.S | 100 jalr $t9
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/external/llvm/test/MC/Mips/mips5/ |
invalid-mips64.s | 14 jalr.hb $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 15 jalr.hb $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/frameworks/compile/mclinker/lib/Target/Mips/ |
MipsRelocationFunctions.h | 30 DECL_MIPS_APPLY_RELOC_FUNC(jalr) \ 75 { &jalr, 37, "R_MIPS_JALR", 32}, \
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MipsRelocator.cpp | 1058 MipsRelocator::Result jalr(MipsRelocationInfo& pReloc, MipsRelocator& pParent) function
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/external/llvm/test/MC/Mips/mips32r2/ |
valid.s | 57 jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] 58 jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
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/external/llvm/test/MC/Mips/mips2/ |
invalid-mips32.s | 15 jalr.hb $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 16 jalr.hb $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/llvm/test/MC/Mips/mips64r2/ |
valid.s | 112 jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] 113 jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
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/external/chromium_org/v8/src/mips/ |
disasm-mips.cc | 635 case JALR: 636 Format(instr, "jalr 'rs"); [all...] |
assembler-mips.h | 563 // to 3 instructions (LUI+ORI+J/JAL/JR/JALR). 741 void jalr(Register rs, Register rd = ra); [all...] |
assembler-mips.cc | 540 ((function_field == JALR) || (rd_field == 0 && (function_field == JR)))); 561 GetRdField(instr) == 0 && GetFunctionField(instr) == JALR; 568 GetRdField(instr) != 0 && GetFunctionField(instr) == JALR; 1432 void Assembler::jalr(Register rs, Register rd) { function in class:v8::Assembler [all...] |
macro-assembler-mips.cc | [all...] |
/external/chromium_org/v8/src/mips64/ |
disasm-mips64.cc | 663 case JALR: 664 Format(instr, "jalr 'rs"); [all...] |
assembler-mips64.cc | 518 ((function_field == JALR) || (rd_field == 0 && (function_field == JR)))); 540 return GetOpcodeField(instr) == SPECIAL && GetFunctionField(instr) == JALR; 1411 void Assembler::jalr(Register rs, Register rd) { function in class:v8::Assembler [all...] |
assembler-mips64.h | 553 // to 3 instructions (LUI+ORI+J/JAL/JR/JALR). 733 void jalr(Register rs, Register rd = ra); [all...] |
codegen-mips64.cc | [all...] |
/external/valgrind/main/none/tests/mips32/ |
branches.stdout.exp | 407 j, jalr, jr 408 J JALR JR :: 6, RSval: 0 409 J JALR JR :: 7, RSval: 1 410 J JALR JR :: 8, RSval: 2 411 J JALR JR :: 9, RSval: 3 412 J JALR JR :: 10, RSval: 4 413 J JALR JR :: 11, RSval: 5 414 J JALR JR :: 12, RSval: 6 415 J JALR JR :: 13, RSval: 7 416 J JALR JR :: 14, RSval: [all...] |
/art/runtime/arch/mips/ |
quick_entrypoints_mips.S | 511 jalr $t9 # call the method [all...] |