| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 308 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
311 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
315 // Complex: to v2f32
316 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
317 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
318 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
319 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
320 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
321 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
339 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 }
[all...] |
| AArch64ISelDAGToDAG.cpp | [all...] |
| AArch64ISelLowering.cpp | 103 addDRTypeForNEON(MVT::v2f32);
464 static MVT RoundingVecTypes[] = {MVT::v2f32, MVT::v4f32, MVT::v2f64 };
482 if (VT == MVT::v2f32) {
497 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 96 v2f32 = 46, // 2 x f32 enumerator in enum:llvm::MVT::SimpleValueType
206 SimpleTy == MVT::v1f64 || SimpleTy == MVT::v2f32);
301 case v2f32:
349 case v2f32:
403 case v2f32:
555 if (NumElements == 2) return MVT::v2f32;
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 192 { ISD::FP_EXTEND, MVT::v2f32, 2 },
242 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
243 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
244 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
245 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
246 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
247 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
455 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1},
477 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1},
|
| ARMISelLowering.cpp | 425 addDRTypeForNEON(MVT::v2f32);
493 // Mark v2f32 intrinsics.
494 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
495 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
496 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
497 setOperationAction(ISD::FPOWI, MVT::v2f32, Expand);
498 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
499 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
500 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
501 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand)
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 161 case MVT::v2f32: return "v2f32";
232 case MVT::v2f32: return VectorType::get(Type::getFloatTy(Context), 2);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 63 (int)MVT::v2f32,
91 (int)MVT::v2f32,
502 FLTTY = MVT::v2f32;
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 63 (int)MVT::v2f32,
91 (int)MVT::v2f32,
502 FLTTY = MVT::v2f32;
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 139 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
140 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
185 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
186 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
210 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
330 MVT::v2f32, MVT::v4f32
[all...] |
| R600ISelLowering.cpp | 39 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom);
146 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom);
689 return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32,
[all...] |
| SIISelLowering.cpp | 44 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 105 case MVT::v2f32: return "MVT::v2f32";
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 64 case MVT::v2f32:
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
