| /external/chromium_org/v8/src/mips64/ |
| simulator-mips64.h | 169 // Coprocessor registers.
396 // Coprocessor Registers.
|
| assembler-mips64.h | 196 // Coprocessor register.
323 // FPU (coprocessor 1) control registers.
[all...] |
| /external/chromium_org/base/ |
| atomicops_internals_arm_gcc.h | 25 // writing a random value to a very specific coprocessor register.
|
| /external/chromium_org/third_party/tcmalloc/chromium/src/windows/ |
| mini_disassembler.h | 55 // -# No support for coprocessor opcodes, MMX, etc.
|
| /external/chromium_org/third_party/tcmalloc/vendor/src/windows/ |
| mini_disassembler.h | 55 // -# No support for coprocessor opcodes, MMX, etc.
|
| /external/chromium_org/v8/src/base/ |
| atomicops_internals_arm_gcc.h | 25 // writing a random value to a very specific coprocessor register.
|
| /external/kernel-headers/original/uapi/asm-generic/ |
| siginfo.h | 180 #define ILL_COPROC (__SI_FAULT|7) /* coprocessor error */
|
| /external/valgrind/main/VEX/pub/ |
| libvex_guest_mips32.h | 124 This register provides read access to the coprocessor 0
|
| libvex_guest_mips64.h | 129 This register provides read access to the coprocessor 0
|
| libvex_guest_arm.h | 154 coprocessor), register set "c13", register 3 (the User
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.11-4.6/sysroot/usr/include/bits/ |
| siginfo.h | 167 ILL_COPROC, /* Coprocessor error. */
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.11-4.8/sysroot/usr/include/bits/ |
| siginfo.h | 167 ILL_COPROC, /* Coprocessor error. */
|
| /external/chromium_org/v8/src/arm/ |
| constants-arm.h | 293 // Coprocessor load/store operand size.
295 Long = 1 << 22, // Long load/store coprocessor.
296 Short = 0 << 22 // Short load/store coprocessor.
|
| assembler-arm.cc | [all...] |
| /external/llvm/test/MC/ARM/ |
| diagnostics.s | 393 @ Out of range coprocessor option immediate.
397 @ CHECK-ERRORS: error: coprocessor option must be an immediate in range [0, 255]
400 @ CHECK-ERRORS: error: coprocessor option must be an immediate in range [0, 255]
|
| /system/core/libpixelflinger/codeflinger/ |
| armreg.h | 162 /* ARM3-specific coprocessor 15 registers */
|
| /external/qemu/disas/ |
| mips.c | 78 The general coprocessor instructions use COPZ. */
152 #define OP_SH_SEL 0 /* Coprocessor select field. */
312 "C" 25 bit coprocessor function code (OP_*_COPZ)
351 Coprocessor instructions:
398 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
399 "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
400 "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
452 /* Modifies coprocessor condition code. */
454 /* Reads coprocessor condition code. */
458 /* Reads coprocessor register other than floating point register. *
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.td | 400 // Coprocessor 2 registers.
404 // Coprocessor 3 registers.
|
| /external/qemu/target-mips/ |
| helper.c | 569 [EXCP_CpU] = "coprocessor unusable",
583 [EXCP_C2E] = "precise coprocessor 2",
|
| /external/chromium_org/v8/src/mips/ |
| assembler-mips.h | 207 // Coprocessor register.
334 // FPU (coprocessor 1) control registers.
856 // --------Coprocessor-instructions----------------
[all...] |
| /external/libcxxabi/src/Unwind/ |
| UnwindRegistersRestore.S | 349 @ So, generate the instruction using the corresponding coprocessor mnemonic.
|
| UnwindRegistersSave.S | 349 @ So, generate the instructions using the corresponding coprocessor mnemonic.
|
| /ndk/sources/cxx-stl/llvm-libc++abi/libcxxabi/src/Unwind/ |
| UnwindRegistersRestore.S | 349 @ So, generate the instruction using the corresponding coprocessor mnemonic.
|
| UnwindRegistersSave.S | 349 @ So, generate the instructions using the corresponding coprocessor mnemonic.
|
| /external/chromium_org/native_client_sdk/doc_generated/reference/sandbox_internals/ |
| arm-32-bit-sandbox.html | [all...] |
