| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.h | 319 void ROTR(int Rd, int Rt, int shft); // mips32r2
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrThumb2.td | 47 [shl,srl,sra,rotr]> {
[all...] |
| ARMInstrThumb.td | [all...] |
| ARMInstrInfo.td | 534 [shl, srl, sra, rotr]> {
545 [shl, srl, sra, rotr]> {
556 [shl,srl,sra,rotr]> {
567 [shl,srl,sra,rotr]> {
[all...] |
| /external/clang/include/clang/Basic/ |
| arm_neon.td | 150 // example: (rotr mask0, 3) -> [4, 5, 6, 0, 1, 2, 3]
151 def rotr;
[all...] |
| /external/llvm/include/llvm/ADT/ |
| APInt.h | 866 APInt LLVM_ATTRIBUTE_UNUSED_RESULT rotr(unsigned rotateAmt) const;
887 APInt LLVM_ATTRIBUTE_UNUSED_RESULT rotr(const APInt &rotateAmt) const;
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetSelectionDAG.td | 334 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
[all...] |
| Target.td | 236 // (rotr GPR, 1) - Rotate N places to the right.
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 99 setOperationAction(ISD::ROTR, MVT::i8, Expand);
101 setOperationAction(ISD::ROTR, MVT::i16, Expand);
[all...] |
| /external/openssl/crypto/modes/asm/ |
| ghash-ia64.pl | 118 .rotr in[3],xi[3],Hi[2]
|
| /external/openssl/crypto/rc4/asm/ |
| rc4-ia64.pl | 475 .rotr Data[4], I[2], IPr[3], SI[3], JP[2], SJ[2], T[2], \\
|
| /external/llvm/lib/Support/ |
| APInt.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 269 // The hardware supports 32-bit ROTR, but not ROTL.
272 setOperationAction(ISD::ROTR, MVT::i64, Expand);
299 setOperationAction(ISD::ROTR, VT, Expand);
[all...] |
| /external/chromium_org/third_party/boringssl/src/crypto/aes/asm/ |
| aes-586.pl | 306 &rotr ($s2,8); # 8,11,10, 9
309 &rotr ($s3,16); # 13,12,15,14
312 &rotr ($s0,16); # 1, 0, 3, 2
488 &rotr ($tmp,16);
493 &rotr ($r2,16+8);
[all...] |
| /external/openssl/crypto/aes/asm/ |
| aes-586.pl | 305 &rotr ($s2,8); # 8,11,10, 9
308 &rotr ($s3,16); # 13,12,15,14
311 &rotr ($s0,16); # 1, 0, 3, 2
493 &rotr ($tmp,16);
495 &rotr ($tmp,8);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| LegalizeVectorOps.cpp | 257 case ISD::ROTR:
[all...] |
| /external/chromium_org/v8/src/mips/ |
| assembler-mips.h | 789 void rotr(Register rd, Register rt, uint16_t sa);
[all...] |
| disasm-mips.cc | 649 Format(instr, "rotr 'rd, 'rt, 'sa");
[all...] |
| /external/chromium_org/v8/src/mips64/ |
| assembler-mips64.h | 801 void rotr(Register rd, Register rt, uint16_t sa);
[all...] |
| disasm-mips64.cc | 694 Format(instr, "rotr 'rd, 'rt, 'sa");
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 311 SHL, SRA, SRL, ROTL, ROTR,
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.td | 600 defm RORV : Shift<0b11, "ror", rotr>;
[all...] |
| /external/qemu/target-mips/ |
| translate.c | 129 OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */
[all...] |
