| /external/chromium_org/base/ |
| cpu.cc | 282 if (has_sse3()) return SSE3;
|
| /external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/ |
| x86cpu.gperf | 313 sse3, x86_cpu_set, CPU_SSE3
|
| gen_x86_insn.py | 42 "SSE3", "SVM", "PadLock", "SSSE3", "SSE41", "SSE42", "SSE4a", "SSE5",
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrFormats.td | 550 // SSE3 Instruction Templates:
552 // S3I - SSE3 instructions with PD prefixes.
553 // S3SI - SSE3 instructions with XS prefix.
554 // S3DI - SSE3 instructions with XD prefix.
[all...] |
| X86TargetTransformInfo.cpp | 137 // TODO: Currently the __builtin_popcount() implementation using SSE3
396 // Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle,
483 // SSE3 doesn't have 'blendps'. The following shuffles are expanded into
512 // Fall-back (SSE3 and SSE2).
[all...] |
| /external/qemu/target-i386/ |
| ops_sse_header.h | 2 * MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI support
|
| /frameworks/compile/libbcc/tools/bcc/ |
| Main.cpp | 135 fv.push_back("+sse3");
|
| /external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/tests/ |
| Makefile.inc | 206 EXTRA_DIST += modules/arch/x86/tests/sse3.asm
207 EXTRA_DIST += modules/arch/x86/tests/sse3.hex
|
| /ndk/docs/text/ |
| CPU-ARCH-ABIS.text | 142 documentation, plus the MMX, SSE, SSE2, SSE3, SSSE3 instruction set
231 documentation, plus the MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1,
|
| /external/clang/lib/Basic/ |
| Targets.cpp | [all...] |
| /external/chromium_org/third_party/libjpeg_turbo/ |
| jpgtest.cxx | 325 printf("Using SSE3 code\n");
|
| tjbench.c | 681 printf(" Force MMX, SSE, SSE2, or SSE3 code paths in the underlying codec\n");
784 printf("Forcing SSE3 code\n\n");
|
| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/ |
| lp_bld_swizzle.c | 177 /* XXX: SSE3 has PSHUFB which should be better than bitmasks, but forcing
|
| /external/clang/docs/ |
| CrossCompilation.rst | 113 * ``-fpu=<fpu-name>``, like SSE3, NEON, controlling the FP unit available
|
| /external/llvm/test/CodeGen/X86/ |
| sse2.ll | 1 ; Tests for SSE2 and below, without SSE3+.
|
| sse3.ll | 1 ; These are tests for SSE3 codegen.
|
| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| lp_bld_swizzle.c | 177 /* XXX: SSE3 has PSHUFB which should be better than bitmasks, but forcing
|
| /external/chromium_org/third_party/re2/benchlog/ |
| benchlog.mini | 32 hw.optional.sse3: 1
70 machdep.cpu.features: FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT PSE36 CLFSH DS ACPI MMX FXSR SSE SSE2 SS HTT TM SSE3 MON DSCPL VMX EST TM2 SSSE3 CX16 TPR PDCM
[all...] |
| /external/regex-re2/benchlog/ |
| benchlog.mini | 32 hw.optional.sse3: 1
70 machdep.cpu.features: FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT PSE36 CLFSH DS ACPI MMX FXSR SSE SSE2 SS HTT TM SSE3 MON DSCPL VMX EST TM2 SSSE3 CX16 TPR PDCM
[all...] |
| /external/chromium_org/third_party/libvpx/source/libvpx/vp9/common/ |
| vp9_rtcd_defs.pl | [all...] |
| /external/valgrind/main/ |
| NEWS.old | 392 3.2.1 adds x86/amd64 support for all SSE3 instructions except monitor
413 106852 x86->IR: fisttp (SSE3)
419 129358 x86->IR: fisttpl (SSE3)
[all...] |
| /external/chromium_org/v8/src/ia32/ |
| assembler-ia32.cc | 62 if (cpu.has_sse3() && FLAG_enable_sse3) supported_ |= 1u << SSE3;
[all...] |
| /external/chromium_org/v8/src/x87/ |
| assembler-x87.cc | [all...] |
| /external/valgrind/main/VEX/pub/ |
| libvex.h | 79 #define VEX_HWCAPS_X86_SSE3 (1<<4) /* SSE3 support (>= Prescott) */
84 #define VEX_HWCAPS_AMD64_SSE3 (1<<5) /* SSE3 support */
[all...] |
| /external/chromium_org/third_party/libvpx/source/libvpx/ |
| configure | 263 sse3
|
