/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
radeon_emulate_branches.c | 76 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY; 77 inst_mov->U.I.DstReg.Index = rc_find_free_temporary(s->C); 78 inst_mov->U.I.DstReg.WriteMask = RC_MASK_X; 82 inst->U.I.SrcReg[0].Index = inst_mov->U.I.DstReg.Index; 166 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY; 167 inst_mov->U.I.DstReg.Index = proxies->Temporary[index].Index; 168 inst_mov->U.I.DstReg.WriteMask = RC_MASK_XYZW; 185 inst_cmp->U.I.DstReg.File = file; 186 inst_cmp->U.I.DstReg.Index = index; 187 inst_cmp->U.I.DstReg.WriteMask = RC_MASK_XYZW [all...] |
radeon_vert_fc.c | 106 build_pred_dst(&new_inst->U.I.DstReg, fc_state); 126 build_pred_dst(&new_inst->U.I.DstReg, fc_state); 140 inst->U.I.DstReg.Pred = RC_PRED_INV; 146 inst->U.I.DstReg.Pred = RC_PRED_SET; 149 build_pred_dst(&inst->U.I.DstReg, fc_state); 160 build_pred_dst(&new_inst->U.I.DstReg, fc_state); 189 inst->U.I.DstReg.Pred = RC_PRED_SET; 205 build_pred_dst(&inst->U.I.DstReg, fc_state); 248 build_pred_dst(&inst->U.I.DstReg, &fc_state); 260 build_pred_dst(&inst->U.I.DstReg, &fc_state) [all...] |
r3xx_fragprog.c | 61 if (inst->DstReg.File != RC_FILE_OUTPUT || inst->DstReg.Index != c->OutputDepth) 64 if (inst->DstReg.WriteMask & RC_MASK_Z) { 65 inst->DstReg.WriteMask = RC_MASK_W; 67 inst->DstReg.WriteMask = 0;
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radeon_dataflow_swizzles.c | 55 mov->U.I.DstReg.File = RC_FILE_TEMPORARY; 56 mov->U.I.DstReg.Index = tempreg; 57 mov->U.I.DstReg.WriteMask = split.Phase[phase];
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radeon_program.h | 79 struct rc_dst_register DstReg;
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radeon_rename_regs.c | 75 if (var->Inst->U.I.DstReg.File != RC_FILE_TEMPORARY) {
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/external/mesa3d/src/gallium/drivers/r300/compiler/ |
radeon_emulate_branches.c | 76 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY; 77 inst_mov->U.I.DstReg.Index = rc_find_free_temporary(s->C); 78 inst_mov->U.I.DstReg.WriteMask = RC_MASK_X; 82 inst->U.I.SrcReg[0].Index = inst_mov->U.I.DstReg.Index; 166 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY; 167 inst_mov->U.I.DstReg.Index = proxies->Temporary[index].Index; 168 inst_mov->U.I.DstReg.WriteMask = RC_MASK_XYZW; 185 inst_cmp->U.I.DstReg.File = file; 186 inst_cmp->U.I.DstReg.Index = index; 187 inst_cmp->U.I.DstReg.WriteMask = RC_MASK_XYZW [all...] |
radeon_vert_fc.c | 106 build_pred_dst(&new_inst->U.I.DstReg, fc_state); 126 build_pred_dst(&new_inst->U.I.DstReg, fc_state); 140 inst->U.I.DstReg.Pred = RC_PRED_INV; 146 inst->U.I.DstReg.Pred = RC_PRED_SET; 149 build_pred_dst(&inst->U.I.DstReg, fc_state); 160 build_pred_dst(&new_inst->U.I.DstReg, fc_state); 189 inst->U.I.DstReg.Pred = RC_PRED_SET; 205 build_pred_dst(&inst->U.I.DstReg, fc_state); 248 build_pred_dst(&inst->U.I.DstReg, &fc_state); 260 build_pred_dst(&inst->U.I.DstReg, &fc_state) [all...] |
r3xx_fragprog.c | 61 if (inst->DstReg.File != RC_FILE_OUTPUT || inst->DstReg.Index != c->OutputDepth) 64 if (inst->DstReg.WriteMask & RC_MASK_Z) { 65 inst->DstReg.WriteMask = RC_MASK_W; 67 inst->DstReg.WriteMask = 0;
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radeon_dataflow_swizzles.c | 55 mov->U.I.DstReg.File = RC_FILE_TEMPORARY; 56 mov->U.I.DstReg.Index = tempreg; 57 mov->U.I.DstReg.WriteMask = split.Phase[phase];
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radeon_program.h | 79 struct rc_dst_register DstReg;
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/tests/ |
rc_test_helpers.c | 241 inst->U.I.DstReg.File = RC_FILE_TEMPORARY; 243 inst->U.I.DstReg.File = RC_FILE_OUTPUT; 251 inst->U.I.DstReg.Index = strtol(tokens.Index.String, NULL, 10); 260 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; 270 inst->U.I.DstReg.WriteMask |= RC_MASK_X; 273 inst->U.I.DstReg.WriteMask |= RC_MASK_Y; 276 inst->U.I.DstReg.WriteMask |= RC_MASK_Z; 279 inst->U.I.DstReg.WriteMask |= RC_MASK_W; 288 inst->U.I.DstReg.File, 289 inst->U.I.DstReg.Index [all...] |
/external/mesa3d/src/gallium/drivers/r300/compiler/tests/ |
rc_test_helpers.c | 241 inst->U.I.DstReg.File = RC_FILE_TEMPORARY; 243 inst->U.I.DstReg.File = RC_FILE_OUTPUT; 251 inst->U.I.DstReg.Index = strtol(tokens.Index.String, NULL, 10); 260 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; 270 inst->U.I.DstReg.WriteMask |= RC_MASK_X; 273 inst->U.I.DstReg.WriteMask |= RC_MASK_Y; 276 inst->U.I.DstReg.WriteMask |= RC_MASK_Z; 279 inst->U.I.DstReg.WriteMask |= RC_MASK_W; 288 inst->U.I.DstReg.File, 289 inst->U.I.DstReg.Index [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
SIInstrInfo.cpp | 52 MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg, 56 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
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/external/mesa3d/src/gallium/drivers/radeon/ |
SIInstrInfo.cpp | 52 MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg, 56 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
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/external/llvm/lib/CodeGen/ |
OptimizePHIs.cpp | 91 unsigned DstReg = MI->getOperand(0).getReg(); 104 if (SrcReg == DstReg) 134 unsigned DstReg = MI->getOperand(0).getReg(); 135 assert(TargetRegisterInfo::isVirtualRegister(DstReg) && 146 for (MachineInstr &UseMI : MRI->use_instructions(DstReg)) {
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TwoAddressInstructionPass.cpp | 132 void scanUses(unsigned DstReg); 339 unsigned &SrcReg, unsigned &DstReg, 342 DstReg = 0; 344 DstReg = MI.getOperand(0).getReg(); 347 DstReg = MI.getOperand(0).getReg(); 353 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); 423 unsigned SrcReg, DstReg; 426 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 434 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) { 441 DstReg = MI.getOperand(ti).getReg() [all...] |
ExpandPostRAPseudos.cpp | 86 unsigned DstReg = MI->getOperand(0).getReg(); 92 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); 94 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) && 112 if (DstReg != InsReg) { 124 // Implicitly define DstReg for subsequent uses. 127 CopyMI->addRegisterDefined(DstReg);
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RegisterCoalescer.cpp | 131 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg, 175 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and 176 /// update the subregister number if it is not zero. If DstReg is a 180 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx); 252 SrcReg = DstReg = 0; 304 // SrcReg will be merged with a sub-register of DstReg. 308 // DstReg will be merged with a sub-register of SrcReg. 320 // Prefer SrcReg to be a sub-register of DstReg. 335 DstReg = Dst; 340 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ExpandPseudoInsts.cpp | 105 const unsigned DstReg = MI.getOperand(0).getReg(); 109 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 110 .addReg(DstReg) 170 const unsigned DstReg = MI.getOperand(0).getReg(); 186 .addReg(DstReg, 188 .addReg(DstReg) 211 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 212 .addReg(DstReg) 353 const unsigned DstReg = MI.getOperand(0).getReg(); 360 .addReg(DstReg, [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonExpandPredSpillCode.cpp | 131 // DstReg = LDriw_pred [R30], ofst. 132 int DstReg = MI->getOperand(0).getReg(); 133 assert(Hexagon::PredRegsRegClass.contains(DstReg) && 154 DstReg).addReg(HEXAGON_RESERVED_REG_2); 163 DstReg).addReg(HEXAGON_RESERVED_REG_2); 169 DstReg).addReg(HEXAGON_RESERVED_REG_2);
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/external/llvm/lib/Target/MSP430/ |
MSP430RegisterInfo.cpp | 143 unsigned DstReg = MI.getOperand(0).getReg(); 145 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::SUB16ri), DstReg) 146 .addReg(DstReg).addImm(-Offset); 148 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg) 149 .addReg(DstReg).addImm(Offset);
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/external/llvm/lib/Target/Mips/ |
MipsSEInstrInfo.cpp | 480 unsigned DstReg = I->getOperand(0).getReg(); 481 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 482 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); 494 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; 503 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 506 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 509 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); 515 unsigned DstReg = I->getOperand(0).getReg() [all...] |
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
brw_program.c | 205 prog->Instructions[i].DstReg.RelAddr && 206 prog->Instructions[i].DstReg.File == PROGRAM_OUTPUT) { 212 if ((prog->Instructions[i].DstReg.RelAddr && 213 prog->Instructions[i].DstReg.File == PROGRAM_TEMPORARY) ||
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/external/llvm/lib/Target/R600/ |
R600InstrInfo.h | 243 unsigned DstReg, 250 unsigned DstReg) const; 254 unsigned DstReg, 259 unsigned DstReg, unsigned SrcReg) const override;
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