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      1 //===-- MSP430RegisterInfo.cpp - MSP430 Register Information --------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the MSP430 implementation of the TargetRegisterInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "MSP430RegisterInfo.h"
     15 #include "MSP430.h"
     16 #include "MSP430MachineFunctionInfo.h"
     17 #include "MSP430TargetMachine.h"
     18 #include "llvm/ADT/BitVector.h"
     19 #include "llvm/CodeGen/MachineFrameInfo.h"
     20 #include "llvm/CodeGen/MachineFunction.h"
     21 #include "llvm/CodeGen/MachineInstrBuilder.h"
     22 #include "llvm/IR/Function.h"
     23 #include "llvm/Support/ErrorHandling.h"
     24 #include "llvm/Target/TargetMachine.h"
     25 #include "llvm/Target/TargetOptions.h"
     26 
     27 using namespace llvm;
     28 
     29 #define DEBUG_TYPE "msp430-reg-info"
     30 
     31 #define GET_REGINFO_TARGET_DESC
     32 #include "MSP430GenRegisterInfo.inc"
     33 
     34 // FIXME: Provide proper call frame setup / destroy opcodes.
     35 MSP430RegisterInfo::MSP430RegisterInfo()
     36   : MSP430GenRegisterInfo(MSP430::PCW) {}
     37 
     38 const MCPhysReg*
     39 MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
     40   const TargetFrameLowering *TFI = MF->getTarget().getFrameLowering();
     41   const Function* F = MF->getFunction();
     42   static const MCPhysReg CalleeSavedRegs[] = {
     43     MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
     44     MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
     45     0
     46   };
     47   static const MCPhysReg CalleeSavedRegsFP[] = {
     48     MSP430::R5W, MSP430::R6W, MSP430::R7W,
     49     MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
     50     0
     51   };
     52   static const MCPhysReg CalleeSavedRegsIntr[] = {
     53     MSP430::FPW,  MSP430::R5W,  MSP430::R6W,  MSP430::R7W,
     54     MSP430::R8W,  MSP430::R9W,  MSP430::R10W, MSP430::R11W,
     55     MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
     56     0
     57   };
     58   static const MCPhysReg CalleeSavedRegsIntrFP[] = {
     59     MSP430::R5W,  MSP430::R6W,  MSP430::R7W,
     60     MSP430::R8W,  MSP430::R9W,  MSP430::R10W, MSP430::R11W,
     61     MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
     62     0
     63   };
     64 
     65   if (TFI->hasFP(*MF))
     66     return (F->getCallingConv() == CallingConv::MSP430_INTR ?
     67             CalleeSavedRegsIntrFP : CalleeSavedRegsFP);
     68   else
     69     return (F->getCallingConv() == CallingConv::MSP430_INTR ?
     70             CalleeSavedRegsIntr : CalleeSavedRegs);
     71 
     72 }
     73 
     74 BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
     75   BitVector Reserved(getNumRegs());
     76   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
     77 
     78   // Mark 4 special registers with subregisters as reserved.
     79   Reserved.set(MSP430::PCB);
     80   Reserved.set(MSP430::SPB);
     81   Reserved.set(MSP430::SRB);
     82   Reserved.set(MSP430::CGB);
     83   Reserved.set(MSP430::PCW);
     84   Reserved.set(MSP430::SPW);
     85   Reserved.set(MSP430::SRW);
     86   Reserved.set(MSP430::CGW);
     87 
     88   // Mark frame pointer as reserved if needed.
     89   if (TFI->hasFP(MF)) {
     90     Reserved.set(MSP430::FPB);
     91     Reserved.set(MSP430::FPW);
     92   }
     93 
     94   return Reserved;
     95 }
     96 
     97 const TargetRegisterClass *
     98 MSP430RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
     99                                                                          const {
    100   return &MSP430::GR16RegClass;
    101 }
    102 
    103 void
    104 MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
    105                                         int SPAdj, unsigned FIOperandNum,
    106                                         RegScavenger *RS) const {
    107   assert(SPAdj == 0 && "Unexpected");
    108 
    109   MachineInstr &MI = *II;
    110   MachineBasicBlock &MBB = *MI.getParent();
    111   MachineFunction &MF = *MBB.getParent();
    112   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    113   DebugLoc dl = MI.getDebugLoc();
    114   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
    115 
    116   unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW);
    117   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
    118 
    119   // Skip the saved PC
    120   Offset += 2;
    121 
    122   if (!TFI->hasFP(MF))
    123     Offset += MF.getFrameInfo()->getStackSize();
    124   else
    125     Offset += 2; // Skip the saved FPW
    126 
    127   // Fold imm into offset
    128   Offset += MI.getOperand(FIOperandNum + 1).getImm();
    129 
    130   if (MI.getOpcode() == MSP430::ADD16ri) {
    131     // This is actually "load effective address" of the stack slot
    132     // instruction. We have only two-address instructions, thus we need to
    133     // expand it into mov + add
    134     const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
    135 
    136     MI.setDesc(TII.get(MSP430::MOV16rr));
    137     MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
    138 
    139     if (Offset == 0)
    140       return;
    141 
    142     // We need to materialize the offset via add instruction.
    143     unsigned DstReg = MI.getOperand(0).getReg();
    144     if (Offset < 0)
    145       BuildMI(MBB, std::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
    146         .addReg(DstReg).addImm(-Offset);
    147     else
    148       BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
    149         .addReg(DstReg).addImm(Offset);
    150 
    151     return;
    152   }
    153 
    154   MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
    155   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
    156 }
    157 
    158 unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
    159   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    160 
    161   return TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW;
    162 }
    163