| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 42 setOperationAction(ISD::AND, MVT::i1, Custom);
44 setOperationAction(ISD::ADD, MVT::i64, Legal);
45 setOperationAction(ISD::ADD, MVT::i32, Legal);
47 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
49 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
53 setOperationAction(ISD::LOAD, MVT::i32, Custom);
54 setOperationAction(ISD::LOAD, MVT::i64, Custom);
56 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
57 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
59 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand)
[all...] |
| AMDILISelDAGToDAG.cpp | 103 if (Addr.getOpcode() == ISD::FrameIndex) {
111 } else if (Addr.getOpcode() == ISD::ADD) {
122 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
123 Addr.getOpcode() == ISD::TargetGlobalAddress) {
131 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
132 Addr.getOpcode() == ISD::TargetGlobalAddress) {
136 if (Addr.getOpcode() == ISD::FrameIndex) {
144 } else if (Addr.getOpcode() == ISD::ADD) {
161 case ISD::FrameIndex:
320 if (Addr.getOpcode() == ISD::TargetExternalSymbol |
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 42 setOperationAction(ISD::AND, MVT::i1, Custom);
44 setOperationAction(ISD::ADD, MVT::i64, Legal);
45 setOperationAction(ISD::ADD, MVT::i32, Legal);
47 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
49 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
53 setOperationAction(ISD::LOAD, MVT::i32, Custom);
54 setOperationAction(ISD::LOAD, MVT::i64, Custom);
56 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
57 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
59 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand)
[all...] |
| AMDILISelDAGToDAG.cpp | 103 if (Addr.getOpcode() == ISD::FrameIndex) {
111 } else if (Addr.getOpcode() == ISD::ADD) {
122 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
123 Addr.getOpcode() == ISD::TargetGlobalAddress) {
131 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
132 Addr.getOpcode() == ISD::TargetGlobalAddress) {
136 if (Addr.getOpcode() == ISD::FrameIndex) {
144 } else if (Addr.getOpcode() == ISD::ADD) {
161 case ISD::FrameIndex:
320 if (Addr.getOpcode() == ISD::TargetExternalSymbol |
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypesGeneric.cpp | 56 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
57 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
66 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
67 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
73 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
74 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
79 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
80 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
90 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
91 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi)
[all...] |
| FastISel.cpp | 192 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
205 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
224 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP,
302 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND,
307 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE,
359 /// which has an opcode which directly corresponds to the given ISD opcode.
375 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
376 ISDOpcode == ISD::XOR))
413 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &
[all...] |
| SelectionDAGBuilder.h | 209 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
219 ISD::CondCode CC;
697 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
698 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
699 void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
701 void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
702 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
703 void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
704 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
705 void visitFRem(const User &I) { visitBinary(I, ISD::FREM);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.cpp | 68 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
75 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
81 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
87 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
109 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
118 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
133 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
140 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
178 Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
180 Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src)
[all...] |
| ARMISelDAGToDAG.cpp | 282 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
334 if (N->getOpcode() != ISD::ADD)
349 if (!isOpcWithIntImmediate(N1.getNode(), ISD::AND, And_imm)) {
350 if (isOpcWithIntImmediate(N0.getNode(), ISD::AND, And_imm))
376 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
395 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32,
398 N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32,
400 N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32,
424 if (Use->getOpcode() == ISD::CopyToReg)
524 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 29 FIRST_NUMBER = ISD::BUILTIN_OP_END,
257 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
355 /// getSetCCResultType - Return the ISD::SETCC ValueType
363 ISD::MemIndexedMode &AM,
521 const SmallVectorImpl<ISD::InputArg> &Ins,
571 const SmallVectorImpl<ISD::InputArg> &Ins,
582 const SmallVectorImpl<ISD::InputArg> &Ins,
588 const SmallVectorImpl<ISD::InputArg> &Ins,
599 const SmallVectorImpl<ISD::OutputArg> &Outs,
605 const SmallVectorImpl<ISD::OutputArg> &Outs
[all...] |
| PPCTargetTransformInfo.cpp | 351 int ISD = TLI->InstructionOpcodeToISD(Opcode);
352 assert(ISD && "Invalid opcode");
367 if (ISD == ISD::INSERT_VECTOR_ELT)
374 if (ISD == ISD::EXTRACT_VECTOR_ELT ||
375 ISD == ISD::INSERT_VECTOR_ELT)
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 190 case ISD::Constant: {
201 case ISD::FrameIndex:
210 case ISD::ADD: {
224 case ISD::OR:
305 ISD::MemIndexedMode AM = LD->getAddressingMode();
306 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD)
358 if (N1.getOpcode() == ISD::LOAD &&
404 case ISD::FrameIndex: {
414 case ISD::LOAD
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 393 ISD::isNormalLoad(LD)) {
591 bool zextval = (LD->getExtensionType() == ISD::ZEXTLOAD);
621 LD->getExtensionType() == ISD::ZEXTLOAD) {
625 LD->getExtensionType() == ISD::SEXTLOAD) {
679 ISD::MemIndexedMode AM = LD->getAddressingMode();
682 if (AM != ISD::UNINDEXED) {
777 if (Base.getOpcode() == ISD::TargetGlobalAddress) {
819 ISD::MemIndexedMode AM = ST->getAddressingMode();
822 if (AM != ISD::UNINDEXED) {
851 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 417 if (Opcode == ISD::TRUNCATE) {
421 if (Opcode == ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) {
433 if (Op0Code == ISD::Constant)
436 if (Op1Code == ISD::Constant)
484 if (Base->getOpcode() == ISD::FrameIndex)
514 if (IndexOpcode == ISD::SIGN_EXTEND ||
515 IndexOpcode == ISD::SIGN_EXTEND_INREG)
535 if (Addr.getOpcode() == ISD::Constant &&
582 else if (Base.getOpcode() == ISD::FrameIndex) {
591 SDValue Trunc = CurDAG->getNode(ISD::TRUNCATE, DL, VT, Base)
[all...] |
| SystemZSelectionDAGInfo.cpp | 114 Dst = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
119 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2);
128 SDValue Dst2 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
133 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2);
148 SDValue DstPlus1 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
184 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i32, IPM,
186 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL,
215 Char = DAG.getNode(ISD::AND, DL, MVT::i32, Char,
217 SDValue Limit = DAG.getNode(ISD::ADD, DL, PtrVT, Src, Length);
273 SDValue Len = DAG.getNode(ISD::SUB, DL, PtrVT, End, Src)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
89 /// getSetCCResultType - Return the ISD::SETCC ValueType
96 const SmallVectorImpl<ISD::InputArg> &Ins,
102 const SmallVectorImpl<ISD::InputArg> &Ins,
108 const SmallVectorImpl<ISD::InputArg> &Ins,
123 const SmallVectorImpl<ISD::OutputArg> &Outs,
128 const SmallVectorImpl<ISD::OutputArg> &Outs,
133 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
133 const SmallVectorImpl<ISD::InputArg> &Ins,
139 const SmallVectorImpl<ISD::OutputArg> &Outs,
141 const SmallVectorImpl<ISD::InputArg> &Ins,
195 const SmallVectorImpl<ISD::InputArg> &Ins,
206 const SmallVectorImpl<ISD::OutputArg> &Outs,
213 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
|
| /external/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 155 ISD::ArgFlagsTy ArgFlags, CCState &State);
162 ISD::ArgFlagsTy &ArgFlags, CCState &State);
264 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
269 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
275 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
280 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
286 SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
291 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
408 int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
|
| SelectionDAG.h | 487 return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
498 return getNode(ISD::CopyToReg, dl, VTs,
507 return getNode(ISD::CopyToReg, dl, VTs,
514 return getNode(ISD::CopyFromReg, dl, VTs, Ops);
524 return getNode(ISD::CopyFromReg, dl, VTs,
528 SDValue getCondCode(ISD::CondCode Cond);
534 SDValue Rnd, SDValue Sat, ISD::CvtCode Code);
536 /// getVectorShuffle - Return an ISD::VECTOR_SHUFFLE node. The number of
600 return getNode(ISD::CALLSEQ_START, DL, VTs, Ops);
615 return getNode(ISD::CALLSEQ_END, DL, NodeTys, Ops)
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 124 static ISD::NodeType getExtendForContent(BooleanContent Content) {
128 return ISD::ANY_EXTEND;
131 return ISD::ZERO_EXTEND;
134 return ISD::SIGN_EXTEND;
167 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
168 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
521 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
554 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 313 if (N.getOpcode() != ISD::LOAD)
325 case ISD::ADD:
326 case ISD::ADDC:
327 case ISD::ADDE:
328 case ISD::AND:
329 case ISD::OR:
330 case ISD::XOR: {
359 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
378 assert(Chain.getOpcode() == ISD::TokenFactor &&
386 CurDAG->getNode(ISD::TokenFactor, SDLoc(Load), MVT::Other, Ops)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 30 // Start the numbering from where ISD NodeType finishes.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
197 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
245 /// getSetCCResultType - get the ISD::SETCC result ValueType
280 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
309 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
325 return DAG.getNode(ISD::ADD, DL, Ty,
360 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
364 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
368 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 28 FIRST_NUMBER = ISD::BUILTIN_OP_END,
90 // Vector bit select: similar to ISD::VSELECT but not all bits within an
166 LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
260 /// getSetCCResultType - Return the ISD::SETCC ValueType
341 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
350 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
357 const SmallVectorImpl<ISD::OutputArg> &Outs,
359 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
376 const SmallVectorImpl<ISD::OutputArg> &Outs,
380 const SmallVectorImpl<ISD::OutputArg> &Outs
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.h | 95 /// from the LLVM IR Function and fixup the ISD:InputArg values before
99 const SmallVectorImpl<ISD::InputArg> &Ins,
100 SmallVectorImpl<ISD::InputArg> &OrigIns) const;
102 const SmallVectorImpl<ISD::InputArg> &Ins) const;
127 const SmallVectorImpl<ISD::OutputArg> &Outs,
167 // AMDIL ISD Opcodes
168 FIRST_NUMBER = ISD::BUILTIN_OP_END,
173 // End AMDIL ISD Opcodes
235 FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
|
| AMDGPUISelDAGToDAG.cpp | 156 if (Addr.getOpcode() == ISD::FrameIndex) {
164 } else if (Addr.getOpcode() == ISD::ADD) {
175 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
176 Addr.getOpcode() == ISD::TargetGlobalAddress) {
184 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
185 Addr.getOpcode() == ISD::TargetGlobalAddress) {
189 if (Addr.getOpcode() == ISD::FrameIndex) {
197 } else if (Addr.getOpcode() == ISD::ADD) {
220 case ISD::ADD:
221 case ISD::SUB:
[all...] |
