| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 208 bool SelectMOV64Imm32(SDValue N, SDValue &Imm);
275 inline SDValue getI8Imm(unsigned Imm) {
276 return CurDAG->getTargetConstant(Imm, MVT::i8);
281 inline SDValue getI32Imm(unsigned Imm) {
282 return CurDAG->getTargetConstant(Imm, MVT::i32);
343 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
344 if (Imm->getAPIntValue().isSignedIntN(8))
[all...] |
| X86FrameLowering.cpp | 59 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
61 if (isInt<8>(Imm))
65 if (isInt<8>(Imm))
71 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
73 if (isInt<8>(Imm))
77 if (isInt<8>(Imm))
[all...] |
| X86RegisterInfo.cpp | 515 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
516 int Offset = FIOffset + Imm;
517 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
|
| X86CodeEmitter.cpp | 788 // 0b01000: XOP map select - 08h instructions with imm byte
789 // 0b01001: XOP map select - 09h instructions with no imm byte
790 // 0b01010: XOP map select - 0Ah instructions with imm dword
[all...] |
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 324 struct ImmOp Imm;
341 Imm = o.Imm;
363 return Imm.Val;
383 return (unsigned) Imm.Val;
388 return (unsigned) Imm.Val;
393 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
398 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
403 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
581 Op->Imm.Val = Val
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 425 // Return true if MI is a shift of type Opcode by Imm bits.
426 static bool isShift(MachineInstr *MI, int Opcode, int64_t Imm) {
429 MI->getOperand(3).getImm() == Imm);
720 uint64_t Imm = MI->getOperand(2).getImm() << And.ImmLSB;
722 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
724 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
[all...] |
| /external/valgrind/main/VEX/priv/ |
| host_x86_defs.c | 164 am->Xam.IR.imm = imm32;
171 am->Xam.IRRS.imm = imm32;
182 return X86AMode_IR( am->Xam.IR.imm, am->Xam.IR.reg );
184 return X86AMode_IRRS( am->Xam.IRRS.imm, am->Xam.IRRS.base,
194 if (am->Xam.IR.imm == 0)
197 vex_printf("0x%x(", am->Xam.IR.imm);
202 vex_printf("0x%x(", am->Xam.IRRS.imm);
246 op->Xrmi.Imm.imm32 = imm32;
265 vex_printf("$0x%x", op->Xrmi.Imm.imm32);
317 op->Xri.Imm.imm32 = imm32
[all...] |
| host_amd64_defs.h | 138 UInt imm; member in struct:__anon15346::__anon15347::__anon15348
142 UInt imm; member in struct:__anon15346::__anon15347::__anon15349
175 } Imm;
210 } Imm;
|
| host_x86_defs.h | 126 UInt imm; member in struct:__anon15828::__anon15829::__anon15830
130 UInt imm; member in struct:__anon15828::__anon15829::__anon15831
163 } Imm;
197 } Imm;
|
| host_mips_isel.c | [all...] |
| host_ppc_defs.h | 249 } Imm;
277 ULong Imm;
525 Pin_AvShlDbl, /* AV shift-left double by imm */
[all...] |
| host_mips_defs.h | 237 } Imm;
408 ULong imm; member in struct:__anon15628::__anon15629::__anon15630
|
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 487 OS << "imm(" << UnfoldedOffset << ')';
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600InstrInfo.cpp | 346 unsigned Imm = MI->getOperand(
348 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Imm));
[all...] |
| R600ControlFlowFinalizer.cpp | 354 int64_t Imm = Srcs[i].second;
356 std::find(Lits.begin(), Lits.end(), Imm);
363 Lits.push_back(Imm);
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 86 inline SDValue getI32Imm(unsigned Imm) {
87 return CurDAG->getTargetConstant(Imm, MVT::i32);
189 inline bool is_so_imm(unsigned Imm) const {
190 return ARM_AM::getSOImmVal(Imm) != -1;
193 inline bool is_so_imm_not(unsigned Imm) const {
194 return ARM_AM::getSOImmVal(~Imm) != -1;
197 inline bool is_t2_so_imm(unsigned Imm) const {
198 return ARM_AM::getT2SOImmVal(Imm) != -1;
201 inline bool is_t2_so_imm_not(unsigned Imm) const {
202 return ARM_AM::getT2SOImmVal(~Imm) != -1
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 554 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
590 // Returns true and sets Imm if:
597 static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
611 Imm = SplatValue;
[all...] |
| MipsSEInstrInfo.cpp | 50 (MI->getOperand(2).isImm()) && // the imm is zero
73 (MI->getOperand(2).isImm()) && // the imm is zero
377 /// result of adding register REG and immediate IMM.
379 MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
393 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
|
| MipsISelLowering.h | 591 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 375 struct ImmOp Imm;
701 return Imm.Val;
793 Op->Imm.Val = Val;
868 OS << "Imm<";
869 Imm.Val->print(OS);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGISel.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/ppp/pppd/plugins/radius/etc/ |
| dictionary.ascend | 262 VALUE Ascend-Token-Immediate Tok-Imm-No 0
263 VALUE Ascend-Token-Immediate Tok-Imm-Yes 1
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
