| /external/llvm/lib/Target/R600/ |
| SIInstrInfo.h | 109 bool isInlineConstant(const APInt &Imm) const;
|
| SIInstrInfo.cpp | 486 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
487 int32_t Val = Imm.getSExtValue();
500 return (APInt::floatToBits(0.0f) == Imm) ||
501 (APInt::floatToBits(1.0f) == Imm) ||
502 (APInt::floatToBits(-1.0f) == Imm) ||
503 (APInt::floatToBits(0.5f) == Imm) ||
504 (APInt::floatToBits(-0.5f) == Imm) ||
505 (APInt::floatToBits(2.0f) == Imm) ||
506 (APInt::floatToBits(-2.0f) == Imm) ||
507 (APInt::floatToBits(4.0f) == Imm) ||
[all...] |
| AMDGPUISelLowering.h | 121 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.h | 77 bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
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| AMDGPUInstrInfo.h | 135 int64_t Imm) const = 0;
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| R600InstrInfo.cpp | 79 unsigned DstReg, int64_t Imm) const
84 MachineInstrBuilder(MI).addImm(Imm);
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| /external/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 52 inline SDValue getI32Imm(unsigned Imm) {
53 return CurDAG->getTargetConstant(Imm, MVT::i32);
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| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 539 unsigned Imm = MI->getOperand(2).getImm();
543 if (Imm & 3 || Imm > 1020)
558 .addImm(Imm / 4); // The tADDrSPi has an implied scale by four.
673 unsigned Imm = MI->getOperand(2).getImm();
675 if (Imm > Limit)
[all...] |
| ARMCodeEmitter.cpp | 335 unsigned getShiftOp(unsigned Imm) const ;
404 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
405 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
[all...] |
| ARMTargetTransformInfo.cpp | 77 unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override;
151 unsigned ARMTTI::getIntImmCost(const APInt &Imm, Type *Ty) const {
158 int32_t SImmVal = Imm.getSExtValue();
159 uint32_t ZImmVal = Imm.getZExtValue();
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| /external/llvm/lib/Target/Mips/ |
| Mips16ISelLowering.cpp | 729 int64_t imm = MI->getOperand(1).getImm(); local
732 if (isUInt<8>(imm))
734 else if ((!ImmSigned && isUInt<16>(imm)) ||
735 (ImmSigned && isInt<16>(imm)))
740 .addImm(imm);
747 (unsigned shortOp, unsigned longOp, int64_t Imm) {
748 if (isUInt<8>(Imm))
750 else if (isInt<16>(Imm))
781 int64_t Imm = MI->getOperand(2).getImm();
782 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
[all...] |
| /external/valgrind/main/VEX/priv/ |
| host_mips_defs.c | 1009 op->Mrh.Imm.syned = syned;
1010 op->Mrh.Imm.imm16 = imm16;
1032 if (op->Mrh.Imm.syned)
1033 vex_printf("%d", (Int) (Short) op->Mrh.Imm.imm16);
1035 vex_printf("%u", (UInt) (UShort) op->Mrh.Imm.imm16);
1181 MIPSInstr *MIPSInstr_LI(HReg dst, ULong imm)
1186 i->Min.LI.imm = imm;
[all...] |
| host_amd64_defs.c | 208 am->Aam.IR.imm = imm32;
215 am->Aam.IRRS.imm = imm32;
226 if (am->Aam.IR.imm == 0)
229 vex_printf("0x%x(", am->Aam.IR.imm);
234 vex_printf("0x%x(", am->Aam.IRRS.imm);
278 op->Armi.Imm.imm32 = imm32;
297 vex_printf("$0x%x", op->Armi.Imm.imm32);
358 op->Ari.Imm.imm32 = imm32;
371 vex_printf("$0x%x", op->Ari.Imm.imm32);
[all...] |
| host_ppc_defs.c | 399 op->Prh.Imm.syned = syned;
400 op->Prh.Imm.imm16 = imm16;
418 if (op->Prh.Imm.syned)
419 vex_printf("%d", (Int)(Short)op->Prh.Imm.imm16);
421 vex_printf("%u", (UInt)(UShort)op->Prh.Imm.imm16);
464 op->Pri.Imm = imm64;
477 vex_printf("0x%llx", dst->Pri.Imm);
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 254 int64_t Imm;
261 IntelExprStateMachine(int64_t imm, bool stoponlbrac, bool addimmprefix) :
263 Scale(1), Imm(imm), Sym(nullptr), StopOnLBrac(stoponlbrac),
271 int64_t getImm() { return Imm + IC.execute(); }
501 IC.pushOperand(IC_IMM, -TmpInt); // Push -Imm.
511 IC.pushOperand(IC_IMM, ~TmpInt); // Push ~Imm.
[all...] |
| X86Operand.h | 61 struct ImmOp Imm;
100 return Imm.Val;
438 Res->Imm.Val = Val;
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| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 175 struct ImmOp Imm;
210 return Imm.Val;
241 case k_Immediate: OS << "Imm: " << getImm() << "\n"; break;
312 Op->Imm.Val = Val;
375 const MCExpr *Imm = Op->getImm();
379 Op->Mem.Off = Imm;
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| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 368 /// can be more efficiently represented with [r+imm].
373 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
454 bool isLegalICmpImmediate(int64_t Imm) const override;
460 bool isLegalAddImmediate(int64_t Imm) const override;
470 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 79 unsigned DstReg, int64_t Imm) const
84 MachineInstrBuilder(MI).addImm(Imm);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 223 int64_t Imm = MO.getImm();
224 O << '#' << Imm;
|
| AArch64ISelLowering.h | 254 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
317 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCTargetDesc.cpp | 341 int64_t Imm = Inst.getOperand(0).getImm();
343 Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.h | 50 void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
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| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 103 const MCExpr *Imm;
148 Op->Imm = Expr;
196 return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
200 return Imm;
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| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.h | 209 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
|
