| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.cpp | 210 unsigned NumOps = Node->getNumOperands();
211 if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
212 Chain = Node->getOperand(NumOps-1).getNode();
[all...] |
| ScheduleDAGRRList.cpp | [all...] |
| LegalizeVectorTypes.cpp | [all...] |
| TargetLowering.cpp | 88 const SDValue *Ops, unsigned NumOps,
93 Args.reserve(NumOps);
96 for (unsigned i = 0; i != NumOps; ++i) {
[all...] |
| LegalizeDAG.cpp | 104 unsigned NumOps, bool isSigned, SDLoc dl);
[all...] |
| SelectionDAGISel.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Scalarizer.cpp | 565 unsigned NumOps = PHI.getNumOperands();
567 Res[I] = Builder.CreatePHI(VT->getElementType(), NumOps,
570 for (unsigned I = 0; I < NumOps; ++I) {
|
| Reassociate.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| AsmWriterEmitter.cpp | 387 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
388 assert(NumOps <= Inst->Operands.size() &&
391 Inst->Operands.begin()+NumOps);
[all...] |
| /external/llvm/lib/CodeGen/ |
| TwoAddressInstructionPass.cpp | 435 for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {
[all...] |
| MachineVerifier.cpp | 749 unsigned NumOps;
750 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
755 NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMConstantIslandPass.cpp | [all...] |
| ARMBaseInstrInfo.cpp | 157 unsigned NumOps = MCID.getNumOperands();
161 const MachineOperand &Offset = MI->getOperand(NumOps-3);
165 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
166 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
624 unsigned NumOps = MCID.getNumOperands();
626 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
[all...] |
| ARMAsmPrinter.cpp | [all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMLoadStoreOptimizer.cpp | [all...] |
| /external/llvm/include/llvm/IR/ |
| Constants.h | 802 ConstantExpr(Type *ty, unsigned Opcode, Use *Ops, unsigned NumOps)
803 : Constant(ty, ConstantExprVal, Ops, NumOps) {
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGNodes.h | [all...] |
| MachineRegisterInfo.h | 193 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
[all...] |
| /external/llvm/lib/Linker/ |
| LinkModules.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 696 unsigned NumOps = Node->getNumOperands();
697 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
698 --NumOps; // Ignore the flag operand.
700 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 566 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
568 for (unsigned i = 0; i < NumOps; ++i, ++I) {
631 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
633 for (unsigned i = 0; i < NumOps; ++i, ++I) {
669 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
670 for (unsigned i = 0; i < NumOps; ++i, ++I) {
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | [all...] |
