| /external/llvm/lib/Target/R600/ |
| SIInstrInfo.h | 26 const SIRegisterInfo RI;
62 return RI;
|
| AMDGPUAsmPrinter.cpp | 151 const R600RegisterInfo * RI =
169 unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
218 const SIRegisterInfo * RI =
291 unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
|
| R600InstrInfo.cpp | 33 RI(st)
37 return RI;
68 unsigned SubRegIndex = RI.getSubRegFromChannel(I);
70 RI.getSubReg(DestReg, SubRegIndex),
71 RI.getSubReg(SrcReg, SubRegIndex))
89 I->isUse() && RI.isPhysRegLiveAcrossClauses(I->getReg()))
367 unsigned Index = RI.getEncodingValue(Reg) & 0xff;
381 unsigned Chan = RI.getHWRegChan(Reg);
460 if (Src.first == GET_REG_INDEX(RI.getEncodingValue(AMDGPU::OQAP))) {
648 unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff
[all...] |
| AMDGPUInstrInfo.cpp | 34 : AMDGPUGenInstrInfo(-1,-1), RI(st), ST(st) { }
37 return RI;
|
| /external/llvm/lib/CodeGen/ |
| LexicalScopes.cpp | 267 for (SmallVectorImpl<InsnRange>::const_iterator RI = MIRanges.begin(),
269 RI != RE; ++RI) {
270 const InsnRange &R = *RI;
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.h | 23 const MipsSERegisterInfo RI;
|
| Mips16InstrInfo.h | 23 const Mips16RegisterInfo RI;
|
| Mips16FrameLowering.cpp | 178 const MipsRegisterInfo &RI = TII.getRegisterInfo();
179 const BitVector Reserved = RI.getReservedRegs(MF);
|
| /external/llvm/lib/Transforms/IPO/ |
| IPConstantPropagation.cpp | 180 if (ReturnInst *RI = dyn_cast<ReturnInst>(BB->getTerminator())) {
190 V = RI->getOperand(0);
192 V = FindInsertedValue(RI->getOperand(0), i);
|
| DeadArgumentElimination.cpp | 412 if (const ReturnInst *RI = dyn_cast<ReturnInst>(V)) {
417 RetOrArg Use = CreateRet(RI->getParent()->getParent(), RetValNum);
516 if (const ReturnInst *RI = dyn_cast<ReturnInst>(BB->getTerminator()))
517 if (RI->getNumOperands() != 0 && RI->getOperand(0)->getType()
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopRerollPass.cpp | 294 for (DenseSet<int>::iterator RI = Reds.begin(), RIE = Reds.end();
295 RI != RIE; ++RI) {
296 int i = *RI;
658 for (DenseSet<int>::iterator RI = Reds.begin(), RIE = Reds.end();
659 RI != RIE; ++RI) {
660 int i = *RI;
705 for (DenseSet<int>::iterator RI = Reds.begin(), RIE = Reds.end();
706 RI != RIE; ++RI)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 29 RI(tm, *this),
35 return RI;
57 unsigned SubRegIndex = RI.getSubRegFromChannel(I);
59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define)
60 .addReg(RI.getSubReg(SrcReg, SubRegIndex))
|
| R600InstrInfo.h | 34 const R600RegisterInfo RI;
|
| /external/clang/lib/Lex/ |
| PreprocessingRecord.cpp | 285 for (pp_iter RI = PreprocessedEntities.end(),
287 RI != Begin && count < 4; --RI, ++count) {
288 pp_iter I = RI;
292 pp_iter insertI = PreprocessedEntities.insert(RI, Entity);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 29 RI(tm, *this),
35 return RI;
57 unsigned SubRegIndex = RI.getSubRegFromChannel(I);
59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define)
60 .addReg(RI.getSubReg(SrcReg, SubRegIndex))
|
| R600InstrInfo.h | 34 const R600RegisterInfo RI;
|
| /external/llvm/include/llvm/Analysis/ |
| RegionInfo.h | 220 RegionInfo* RI;
255 /// @param RI The region info object that is managing this region.
259 Region(BasicBlock *Entry, BasicBlock *Exit, RegionInfo* RI,
362 return RI;
|
| /external/llvm/lib/MC/MCAnalysis/ |
| MCObjectSymbolizer.cpp | 230 AddrToRelocMap::const_iterator RI = AddrToReloc.find(Addr);
231 if (RI == AddrToReloc.end())
233 return &RI->second;
|
| /art/compiler/dex/quick/x86/ |
| x86_lir.h | 399 // RI - Register Immediate - opcode reg, #immediate
410 opcode ## 8RI, opcode ## 8MI, opcode ## 8AI, opcode ## 8TI, \
413 opcode ## 16RI, opcode ## 16MI, opcode ## 16AI, opcode ## 16TI, \
417 opcode ## 32RI, opcode ## 32MI, opcode ## 32AI, opcode ## 32TI, \
421 opcode ## 64RI, opcode ## 64MI, opcode ## 64AI, opcode ## 64TI, \
469 opcode ## 8RI, opcode ## 8MI, opcode ## 8AI, \
471 opcode ## 16RI, opcode ## 16MI, opcode ## 16AI, \
473 opcode ## 32RI, opcode ## 32MI, opcode ## 32AI, \
475 opcode ## 64RI, opcode ## 64MI, opcode ## 64AI, \
499 UnaryOpcode(kX86Test, RI, MI, AI)
[all...] |
| /external/llvm/include/llvm/Transforms/Utils/ |
| BasicBlockUtils.h | 183 ReturnInst *FoldReturnIntoUncondBranch(ReturnInst *RI, BasicBlock *BB,
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 24 : ARMBaseInstrInfo(STI), RI(STI) {
|
| /external/llvm/utils/TableGen/ |
| FastISelEmitter.cpp | 607 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
608 RI != RE; ++RI) {
609 MVT::SimpleValueType RetVT = RI->first;
610 const PredMap &PM = RI->second;
682 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
683 RI != RE; ++RI) {
684 MVT::SimpleValueType RetVT = RI->first;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.h | 36 const AArch64RegisterInfo RI;
45 const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.h | 32 const HexagonRegisterInfo RI;
43 const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.h | 69 const PPCRegisterInfo RI;
89 const PPCRegisterInfo &getRegisterInfo() const { return RI; }
|
