| /external/llvm/lib/Target/Mips/ |
| MipsConstantIslandPass.cpp | 348 const Mips16InstrInfo *TII;
458 TII = (const Mips16InstrInfo*)MF->getTarget().getInstrInfo();
580 BuildMI(*BB, InsAt, DebugLoc(), TII->get(Mips::CONSTPOOL_ENTRY))
822 BBI.Size += TII->GetInstSizeInBytes(I);
840 Offset += TII->GetInstSizeInBytes(I);
896 BuildMI(OrigBB, DebugLoc(), TII->get(Mips::Bimm16)).addMBB(NewBB);
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIInsertWaits.cpp | 49 const SIInstrInfo *TII;
100 TII(nullptr),
125 uint64_t TSFlags = TII->get(MI.getOpcode()).TSFlags;
137 if (TII->isSMRD(MI.getOpcode())) {
298 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
349 TII = static_cast<const SIInstrInfo*>(MF.getTarget().getInstrInfo());
|
| R600OptimizeVectorRegisters.cpp | 87 const R600InstrInfo *TII;
111 TII(nullptr) { }
133 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
195 MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::INSERT_SUBREG),
212 Pos = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::COPY), Reg)
249 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
317 TII = static_cast<const R600InstrInfo *>(Fn.getTarget().getInstrInfo());
330 if (TII->get(MI->getOpcode()).TSFlags & R600_InstFlag::TEX_INST) {
|
| SIRegisterInfo.cpp | 30 const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
31 TII->reserveIndirectRegisters(Reserved, MF);
|
| SIISelLowering.cpp | 283 const SIInstrInfo *TII =
285 return TII->isInlineConstant(Imm);
461 const SIInstrInfo *TII =
475 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo)
477 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo)
479 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi)
481 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
486 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
496 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64), DestReg)
512 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::SI_RegisterStore)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIAssignInterpRegs.cpp | 126 const TargetInstrInfo * TII = TM.getInstrInfo();
131 TII->get(TargetOpcode::COPY), virtReg)
|
| SIISelLowering.h | 24 const SIInstrInfo * TII;
|
| /external/llvm/lib/Target/ARM/ |
| ARMConstantIslandPass.cpp | 260 const ARMBaseInstrInfo *TII;
385 TII = (const ARMBaseInstrInfo*)MF->getTarget().getInstrInfo();
546 BuildMI(*BB, InsAt, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
807 BBI.Size += TII->GetInstSizeInBytes(I);
838 Offset += TII->GetInstSizeInBytes(I);
[all...] |
| MLxExpansionPass.cpp | 51 const ARMBaseInstrInfo *TII;
221 if (TII->isFpMLxInstruction(DefMI->getOpcode())) {
256 if (TII->canCauseFpMLxStall(NextMI->getOpcode())) {
287 const MCInstrDesc &MCID1 = TII->get(MulOpc);
288 const MCInstrDesc &MCID2 = TII->get(AddSubOpc);
291 TII->getRegClass(MCID1, 0, TRI, MF));
362 if (!TII->isFpMLxInstruction(MCID.getOpcode(),
381 TII = static_cast<const ARMBaseInstrInfo*>(Fn.getTarget().getInstrInfo());
|
| ARMExpandPseudoInsts.cpp | 46 const ARMBaseInstrInfo *TII;
390 TII->get(TableEntry->RealOpc));
455 TII->get(TableEntry->RealOpc));
509 TII->get(TableEntry->RealOpc));
592 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
[all...] |
| ARMLoadStoreOptimizer.cpp | 68 const TargetInstrInfo *TII;
134 const TargetInstrInfo *TII,
386 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII->get(ARM::tSUBi8), Base))
404 AddDefaultT1CC(BuildMI(MBB, --MBBI, dl, TII->get(ARM::tSUBi8), Base))
479 BuildMI(MBB, MBBI, dl, TII->get(ARM::tMOVr), NewBase)
483 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase))
487 BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase)
522 MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode));
535 MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode));
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIAssignInterpRegs.cpp | 126 const TargetInstrInfo * TII = TM.getInstrInfo();
131 TII->get(TargetOpcode::COPY), virtReg)
|
| SIISelLowering.h | 24 const SIInstrInfo * TII;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 132 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
176 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
221 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
293 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
331 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
335 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
455 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
493 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
503 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg)
[all...] |
| ScheduleDAGRRList.cpp | 278 const TargetInstrInfo *TII,
308 const MCInstrDesc Desc = TII->get(Opcode);
309 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF);
410 const TargetInstrInfo *TII) {
420 if (IsChainDependent(N->getOperand(i).getNode(), Inner, NestLevel, TII))
427 (unsigned)TII->getCallFrameDestroyOpcode()) {
430 (unsigned)TII->getCallFrameSetupOpcode()) {
460 const TargetInstrInfo *TII) {
472 MyNestLevel, MyMaxNest, TII))
485 (unsigned)TII->getCallFrameDestroyOpcode())
[all...] |
| /external/llvm/lib/CodeGen/ |
| EarlyIfConversion.cpp | 82 const TargetInstrInfo *TII;
156 TII = MF.getTarget().getInstrInfo();
223 if (!I->isSafeToMove(TII, nullptr, DontMoveAcrossStore)) {
389 if (TII->AnalyzeBranch(*Head, TBB, FBB, Cond)) {
423 if (!TII->canInsertSelect(*Head, Cond, PI.TReg, PI.FReg,
464 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
485 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
541 TII->RemoveBranch(*Head);
568 TII->InsertBranch(*Head, Tail, nullptr, EmptyCond, HeadDL);
581 const TargetInstrInfo *TII;
[all...] |
| CriticalAntiDepBreaker.h | 37 const TargetInstrInfo *TII;
|
| LiveRangeEdit.cpp | 56 if (!TII.isTriviallyReMaterializable(DefMI, aa))
138 if (cheapAsAMove && !TII.isAsCheapAsAMove(RM.OrigMI))
155 TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
201 if (!DefMI->isSafeToMove(&TII, nullptr, SawStore))
211 MachineInstr *FoldMI = TII.foldMemoryOperand(UseMI, Ops, DefMI);
240 if (!MI->isSafeToMove(&TII, nullptr, SawStore)) {
303 MI->setDesc(TII.get(TargetOpcode::KILL));
|
| TwoAddressInstructionPass.cpp | 72 const TargetInstrInfo *TII;
188 if (!MI->isSafeToMove(TII, AA, SeenStore))
338 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
403 const TargetInstrInfo *TII,
426 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
453 const TargetInstrInfo *TII,
464 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
578 MachineInstr *NewMI = TII->commuteInstruction(MI);
626 MachineInstr *NewMI = TII->convertToThreeAddress(MFI, mi, LV);
667 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy
[all...] |
| ExecutionDepsFix.cpp | 133 const TargetInstrInfo *TII;
311 TII->setExecutionDomain(dv->Instrs.pop_back_val(), domain);
452 std::pair<uint16_t, uint16_t> DomP = TII->getExecutionDomain(MI);
500 unsigned Pref = TII->getUndefRegClearance(MI, OpNum, TRI);
526 unsigned Pref = TII->getPartialRegUpdateClearance(MI, i, TRI);
528 TII->breakPartialRegDependency(MI, i, TRI);
564 TII->breakPartialRegDependency(UndefMI, OpIdx, TRI);
637 TII->setExecutionDomain(mi, domain);
716 TII = MF->getTarget().getInstrInfo();
|
| TailDuplication.cpp | 63 const TargetInstrInfo *TII;
138 TII = MF.getTarget().getInstrInfo();
432 MachineInstr *NewMI = TII->duplicate(MI, MF);
660 if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true))
691 if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true))
729 TII->RemoveBranch(*PredBB);
732 TII->InsertBranch(*PredBB, PredTBB, PredFBB, PredCond, DebugLoc());
780 if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true))
794 TII->RemoveBranch(*PredBB);
835 TII->get(TargetOpcode::COPY)
[all...] |
| MachineSink.cpp | 47 const TargetInstrInfo *TII;
217 TII = TM.getInstrInfo();
295 if (!MI->isCopy() && !TII->isAsCheapAsAMove(MI))
512 if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg)))
595 if (!MI->isSafeToMove(TII, AA, SawStore))
636 if (!MI->isSafeToMove(TII, AA, store)) {
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonVLIWPacketizer.cpp | 194 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
242 if (TII->isSchedulingBoundary(std::prev(I), MBB, Fn))
276 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
292 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
306 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
326 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
406 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
414 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
437 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
450 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 134 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
136 MI.setDesc(TII.get(MSP430::MOV16rr));
145 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
148 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
