| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | [all...] |
| MSP430InstrInfo.cpp | 310 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
311 return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
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| /external/llvm/include/llvm/CodeGen/ |
| MachineTraceMetrics.h | 69 const TargetInstrInfo *TII;
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| FastISel.h | 59 const TargetInstrInfo &TII;
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| LiveIntervalAnalysis.h | 55 const TargetInstrInfo* TII;
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| /external/llvm/lib/CodeGen/ |
| PostRASchedulerList.cpp | 82 const TargetInstrInfo *TII;
252 TII = Fn.getTarget().getInstrInfo();
317 if (MI->isCall() || TII->isSchedulingBoundary(MI, MBB, Fn)) {
649 TII->insertNoop(*BB, RegionEnd);
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| ScoreboardHazardRecognizer.cpp | 187 if (DAG->TII->isZeroCost(MCID->Opcode))
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| MachineInstrBundle.cpp | 107 const TargetInstrInfo *TII = TM.getInstrInfo();
111 TII->get(TargetOpcode::BUNDLE));
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| MachineTraceMetrics.cpp | 41 : MachineFunctionPass(ID), MF(nullptr), TII(nullptr), TRI(nullptr),
55 TII = MF->getTarget().getInstrInfo();
61 SchedModel.init(*ST.getSchedModel(), &ST, TII);
[all...] |
| RegAllocFast.cpp | 60 const TargetInstrInfo *TII;
291 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
313 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::DBG_VALUE))
630 TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, RC, TRI);
870 TII->get(TargetOpcode::DBG_VALUE)
[all...] |
| MachineInstr.cpp | [all...] |
| MachineVerifier.cpp | 68 const TargetInstrInfo *TII;
295 TII = TM->getInstrInfo();
557 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
581 !TII->isPredicated(&MBB->back())) {
720 if (MI->isTerminator() && !TII->isPredicated(MI)) {
811 if (!TII->verifyInstruction(MI, ErrorInfo))
[all...] |
| RegisterCoalescer.cpp | 83 const TargetInstrInfo* TII;
603 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
642 MachineInstr *NewMI = TII->commuteInstruction(DefMI);
754 if (!TII->isAsCheapAsAMove(DefMI))
756 if (!TII->isTriviallyReMaterializable(DefMI, AA))
759 if (!DefMI->isSafeToMove(TII, AA, SawStore))
778 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF);
803 TII->reMaterialize(*MBB, MII, DstReg, SrcIdx, DefMI, *TRI);
[all...] |
| AggressiveAntiDepBreaker.cpp | 122 TII(MF.getTarget().getInstrInfo()),
369 TII->isPredicated(MI)) {
388 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
446 TII->isPredicated(MI);
472 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
[all...] |
| TargetInstrInfo.cpp | 383 const TargetInstrInfo &TII) {
408 MF.CreateMachineInstr(TII.get(MI->getOpcode()), MI->getDebugLoc(), true);
423 bool Valid = TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize,
566 const TargetInstrInfo &TII = *TM.getInstrInfo();
585 if (TII.isLoadFromStackSlot(MI, FrameIdx) &&
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| MachineScheduler.cpp | 374 const TargetInstrInfo *TII,
376 return MI->isCall() || TII->isSchedulingBoundary(MI, MBB, *MF);
381 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
420 isSchedBoundary(std::prev(RegionEnd), MBB, MF, TII, IsPostRA)) {
431 if (isSchedBoundary(std::prev(I), MBB, MF, TII, IsPostRA))
[all...] |
| ScheduleDAG.cpp | 39 TII(TM.getInstrInfo()),
60 return &TII->get(Node->getMachineOpcode());
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| /external/llvm/lib/Target/Mips/ |
| MipsDelaySlotFiller.cpp | 518 const MipsInstrInfo *TII =
520 BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
669 const MipsInstrInfo *TII =
676 TII->AnalyzeBranch(MBB, TrueBB, FalseBB, Cond, false, BranchInstrs);
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| /external/llvm/lib/Target/R600/ |
| AMDILCFGStructurizer.cpp | 138 MachineFunctionPass(ID), TII(nullptr), TRI(nullptr) {
163 TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
164 TRI = &TII->getRegisterInfo();
184 const R600InstrInfo *TII;
471 ->CreateMachineInstr(TII->get(NewOpcode), DL);
480 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL);
494 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DebugLoc());
506 MachineInstr *NewMI = MF->CreateMachineInstr(TII->get(NewOpcode), DL);
518 MachineInstr *NewInstr = MF->CreateMachineInstr(TII->get(NewOpcode), DL);
529 MF->CreateMachineInstr(TII->get(NewOpcode), DebugLoc())
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGFast.cpp | 239 if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
258 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
435 const TargetInstrInfo *TII) {
436 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
514 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
575 EVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
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| FunctionLoweringInfo.cpp | 211 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
213 BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 449 const HexagonInstrInfo *TII =
451 if (TII->isValidAutoIncImm(LoadedVT, Val)) {
516 const HexagonInstrInfo *TII =
518 if (TII->isValidAutoIncImm(LoadedVT, Val)) {
594 const HexagonInstrInfo *TII =
597 if (TII->isValidAutoIncImm(LoadedVT, Val))
602 if (TII->isValidAutoIncImm(LoadedVT, Val))
607 if (TII->isValidAutoIncImm(LoadedVT, Val))
612 if (TII->isValidAutoIncImm(LoadedVT, Val))
629 if (TII->isValidAutoIncImm(LoadedVT, Val))
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 99 assert(DAG->TII && "No InstrInfo?");
[all...] |
| PPCISelLowering.cpp | [all...] |
| PPCISelDAGToDAG.cpp | 235 const TargetInstrInfo &TII = *TM.getInstrInfo();
243 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
244 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
246 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
260 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
271 const TargetInstrInfo &TII = *TM.getInstrInfo();
279 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
280 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
283 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
284 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg)
[all...] |
