| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
| AMDGPUMCTargetDesc.h | 39 MCAsmBackend *createAMDGPUAsmBackend(const Target &T, StringRef TT);
|
| /external/clang/test/CXX/temp/temp.type/ |
| p1-0x.cpp | 4 template<template<class> class TT> struct X { };
|
| /external/clang/test/SemaCXX/ |
| access.cpp | 81 template<template<int> class T> friend struct TT;
88 template<template<A::I> class T> struct TT {
92 template struct TT<B>;
94 template struct TT<D>;
|
| /external/llvm/lib/MC/ |
| MCRelocationInfo.cpp | 37 MCRelocationInfo *llvm::createMCRelocationInfo(StringRef TT, MCContext &Ctx) {
|
| /external/llvm/lib/Target/NVPTX/MCTargetDesc/ |
| NVPTXMCTargetDesc.cpp | 40 static MCRegisterInfo *createNVPTXMCRegisterInfo(StringRef TT) {
48 createNVPTXMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) {
50 InitNVPTXMCSubtargetInfo(X, TT, CPU, FS);
55 StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) {
|
| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| AMDGPUMCTargetDesc.h | 39 MCAsmBackend *createAMDGPUAsmBackend(const Target &T, StringRef TT);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetMachine.h | 29 AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU,
68 AArch64leTargetMachine(const Target &T, StringRef TT, StringRef CPU,
79 AArch64beTargetMachine(const Target &T, StringRef TT, StringRef CPU,
|
| AArch64Subtarget.cpp | 44 AArch64Subtarget::AArch64Subtarget(const std::string &TT,
48 : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
51 TargetTriple(TT),
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXSubtarget.cpp | 56 NVPTXSubtarget::NVPTXSubtarget(const std::string &TT, const std::string &CPU,
59 : NVPTXGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), PTXVersion(0),
64 Triple T(TT);
|
| NVPTXTargetMachine.cpp | 69 NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, StringRef TT,
74 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
75 Subtarget(TT, CPU, FS, *this, is64bit) {
82 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
85 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
90 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
93 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
|
| /external/llvm/lib/Target/Sparc/ |
| SparcTargetMachine.h | 26 SparcTargetMachine(const Target &T, StringRef TT,
62 SparcV8TargetMachine(const Target &T, StringRef TT,
74 SparcV9TargetMachine(const Target &T, StringRef TT,
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZSubtarget.cpp | 40 SystemZSubtarget::SystemZSubtarget(const std::string &TT,
44 : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
47 TargetTriple(TT),
|
| SystemZTargetMachine.cpp | 22 SystemZTargetMachine::SystemZTargetMachine(const Target &T, StringRef TT,
27 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
28 Subtarget(TT, CPU, FS, *this) {
|
| /external/llvm/lib/Target/XCore/ |
| XCoreTargetMachine.cpp | 23 XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
29 Subtarget(TT, CPU, FS, *this) {
|
| /ndk/tests/device/issue39680-chrono-resolution/jni/ |
| issue39680-chrono-resolution.cpp | 48 typedef typename ratio_multiply<P,kilo>::type TT;
49 cout << fixed << double(TT::num)/TT::den
|
| /external/clang/test/SemaTemplate/ |
| dependent-base-classes.cpp | 21 template <class TT>
23 typedef typename A<TT>::type type;
26 template <class TT>
27 struct FI : II<TT>
32 template <class TT>
35 C<typename FI2::type> a; // expected-error{{no type named 'type' in 'FI2<TT>'}}
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCTargetDesc.cpp | 45 std::string X86_MC::ParseX86Triple(StringRef TT) {
46 Triple TheTriple(TT);
200 unsigned X86_MC::getDwarfRegFlavour(Triple TT, bool isEH) {
201 if (TT.getArch() == Triple::x86_64)
204 if (TT.isOSDarwin())
206 if (TT.isOSCygMing())
220 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
222 std::string ArchFS = X86_MC::ParseX86Triple(TT);
235 InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
245 static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCTargetDesc.cpp | 46 static inline StringRef selectMipsCPU(StringRef TT, StringRef CPU) {
48 Triple TheTriple(TT);
64 static MCRegisterInfo *createMipsMCRegisterInfo(StringRef TT) {
70 static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
72 CPU = selectMipsCPU(TT, CPU);
74 InitMipsMCSubtargetInfo(X, TT, CPU, FS);
78 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
79 MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
88 static MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM,
109 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
[all...] |
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCTargetDesc.cpp | 50 static MCRegisterInfo *createPPCMCRegisterInfo(StringRef TT) {
51 Triple TheTriple(TT);
62 static MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU,
65 InitPPCMCSubtargetInfo(X, TT, CPU, FS);
69 static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
70 Triple TheTriple(TT);
89 static MCCodeGenInfo *createPPCMCCodeGenInfo(StringRef TT, Reloc::Model RM,
95 Triple T(TT);
102 Triple T(TT);
157 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
[all...] |
| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| SparcMCTargetDesc.cpp | 37 StringRef TT) {
38 MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT);
46 StringRef TT) {
47 MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT);
60 static MCRegisterInfo *createSparcMCRegisterInfo(StringRef TT) {
66 static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU,
69 Triple TheTriple(TT);
72 InitSparcMCSubtargetInfo(X, TT, CPU, FS);
87 static MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM,
104 static MCCodeGenInfo *createSparcV9MCCodeGenInfo(StringRef TT, Reloc::Model RM
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetMachine.h | 28 ARMBaseTargetMachine(const Target &T, StringRef TT,
73 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
83 ARMLETargetMachine(const Target &T, StringRef TT,
94 ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
106 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
116 ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU,
127 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
|
| /external/llvm/lib/Target/Mips/ |
| MipsTargetMachine.cpp | 53 MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
58 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
59 Subtarget(TT, CPU, FS, isLittle, RM, this) {
66 MipsebTargetMachine(const Target &T, StringRef TT,
70 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
75 MipselTargetMachine(const Target &T, StringRef TT,
79 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCTargetMachine.cpp | 40 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
44 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
45 Subtarget(TT, CPU, FS, *this, is64Bit, OL) {
51 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
56 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
61 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
66 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
|
| /external/llvm/lib/Target/XCore/MCTargetDesc/ |
| XCoreMCTargetDesc.cpp | 43 static MCRegisterInfo *createXCoreMCRegisterInfo(StringRef TT) {
49 static MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU,
52 InitXCoreMCSubtargetInfo(X, TT, CPU, FS);
57 StringRef TT) {
58 MCAsmInfo *MAI = new XCoreMCAsmInfo(TT);
67 static MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM,
|
| /external/llvm/lib/ExecutionEngine/ |
| TargetSelect.cpp | 29 Triple TT;
34 TT.setTriple(M->getTargetTriple());
36 return selectTarget(TT, MArch, MCPU, MAttrs);
|
