| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 53 MI->getOperand(2).getImm() == 0) {
74 MI->getOperand(1).getImm() == 0) {
182 SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
246 unsigned CC = Cond[0].getImm();
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 73 MI->getOperand(FIOperandNum + 1).getImm());
|
| SystemZShortenInst.cpp | 85 uint64_t Imm = MI.getOperand(1).getImm();
|
| /external/llvm/lib/Target/XCore/ |
| XCoreAsmPrinter.cpp | 220 O << MO.getImm();
277 if (MI->getOperand(2).getImm() == 0) {
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 116 uint64_t CalleePopAmount = IsDestroy ? I->getOperand(1).getImm() : 0;
122 int64_t Amount = I->getOperand(0).getImm();
252 MBBI->getOperand(4).getImm() < 0 &&
253 (MBBI->getOperand(4).getImm() & 1) == 0);
257 // by addding that offset - 16 = -getImm()*8 - 2*8 = -(getImm() + 2) * 8.
258 FPOffset = -(MBBI->getOperand(4).getImm() + 2) * 8;
456 ArgumentPopSize = StackAdjust.getImm();
[all...] |
| AArch64MCInstLower.cpp | 168 MCOp = MCOperand::CreateImm(MO.getImm());
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 271 int64_t getImm() { return Imm + IC.execute(); }
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIInstrInfo.cpp | 324 unsigned FrameIndex = MI->getOperand(2).getImm();
351 unsigned FrameIndex = MI->getOperand(2).getImm();
390 AMDGPU::OpName::abs)).getImm() ||
392 AMDGPU::OpName::neg)).getImm()))
397 MI->getOperand(1).ChangeToImmediate(MI->getOperand(2).getImm());
513 return isInlineConstant(APInt(32, MO.getImm(), true));
536 return Op0.getImm() == Op1.getImm();
814 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
816 return MachineOperand::CreateImm(Op.getImm() >> 32)
[all...] |
| SILowerControlFlow.cpp | 310 if (Op.isImm() ? (Op.getImm() & 0x80000000) :
406 unsigned Off = MI.getOperand(4).getImm();
426 unsigned Off = MI.getOperand(4).getImm();
|
| R600OptimizeVectorRegisters.cpp | 70 unsigned Chan = Instr->getOperand(i + 1).getImm();
254 unsigned Swizzle = MI.getOperand(i + Offset).getImm() + 1;
|
| R600Packetizer.cpp | 91 if (OperandIdx > -1 && BI->getOperand(OperandIdx).getImm() == 0)
357 (MI->getOpcode() == AMDGPU::CF_ALU && !MI->getOperand(8).getImm())) {
|
| /external/llvm/lib/Target/Mips/ |
| MipsConstantIslandPass.cpp | [all...] |
| Mips16FrameLowering.cpp | 151 int64_t Amount = I->getOperand(0).getImm();
|
| MipsMCInstLower.cpp | 139 return MCOperand::CreateImm(MO.getImm() + offset);
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 637 const MCExpr *Expr = getImm();
661 return isImm() && dyn_cast<MCConstantExpr>(getImm());
699 const MCExpr *getImm() const {
705 const MCExpr *Val = getImm();
921 if (!isIntN(inMicroMipsMode() ? 17 : 18, Offset.getImm()))
923 if (OffsetToAlignment(Offset.getImm(),
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMConstantIslandPass.cpp | [all...] |
| MLxExpansionPass.cpp | 282 unsigned LaneImm = HasLane ? MI->getOperand(4).getImm() : 0;
284 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm();
|
| /external/llvm/lib/Target/X86/ |
| X86CodeEmitter.cpp | 475 DispVal = Op3.getImm();
574 unsigned SS = SSTable[Scale.getImm()];
[all...] |
| X86FrameLowering.cpp | 218 *NumBytes += PI->getOperand(2).getImm();
224 *NumBytes -= PI->getOperand(2).getImm();
248 *NumBytes -= NI->getOperand(2).getImm();
255 *NumBytes += NI->getOperand(2).getImm();
282 Offset += PI->getOperand(2).getImm();
288 Offset -= PI->getOperand(2).getImm();
[all...] |
| /external/llvm/lib/CodeGen/ |
| PeepholeOptimizer.cpp | [all...] |
| ExpandPostRAPseudos.cpp | 89 unsigned SubIdx = MI->getOperand(3).getImm();
|
| PrologEpilogInserter.cpp | 211 unsigned Size = I->getOperand(0).getImm();
217 unsigned ExtraInfo = I->getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
759 int Size = I->getOperand(0).getImm();
793 Offset.setImm(Offset.getImm() +
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonNewValueJump.cpp | 228 int64_t v = MI->getOperand(2).getImm();
502 cmpOp2 = MI->getOperand(2).getImm();
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXAsmPrinter.cpp | 380 lowerImageHandleSymbol(MO.getImm(), MCOp);
384 lowerImageHandleSymbol(MO.getImm(), MCOp);
407 lowerImageHandleSymbol(MO.getImm(), MCOp);
430 lowerImageHandleSymbol(MO.getImm(), MCOp);
453 lowerImageHandleSymbol(MO.getImm(), MCOp);
551 lowerImageHandleSymbol(MO.getImm(), MCOp);
573 lowerImageHandleSymbol(MO.getImm(), MCOp);
630 MCOp = MCOperand::CreateImm(MO.getImm());
922 int Imm = (int) MO.getImm();
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 128 Offset += MI.getOperand(FIOperandNum + 1).getImm();
|
