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  /external/llvm/lib/Target/X86/Disassembler/
X86DisassemblerDecoderCommon.h 81 ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \
89 ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \
91 ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \
102 ENUM_ENTRY(IC_64BIT_REXW_XS, 6, "OPSIZE could mean a different " \
112 ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \
116 ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \
120 ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \
124 ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize") \
128 ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \
132 ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \
    [all...]
  /external/llvm/utils/TableGen/
X86RecognizableInstr.h 51 /// The OpSize field from the record
52 uint8_t OpSize;
118 /// @param OpSize Indicates the operand size of the instruction.
119 /// If register size does not match OpSize, then
123 bool hasREX_WPrefix, uint8_t OpSize);
130 /// @param OpSize - Indicates whether this is an OpSize16 instruction.
134 uint8_t OpSize);
139 uint8_t OpSize);
144 uint8_t OpSize);
146 uint8_t OpSize);
    [all...]
X86RecognizableInstr.cpp 194 OpSize = byteFromRec(Rec, "OpSizeBits");
402 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
404 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
406 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
408 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
425 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
427 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
429 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
450 uint8_t OpSize)) {
468 OpSize);
    [all...]
DisassemblerEmitter.cpp 38 /// instruction with an OPSIZE prefix and an XS prefix decodes the same way in
39 /// all cases as a 64-bit instruction with only OPSIZE set. (The XS prefix
  /art/compiler/dex/quick/arm/
codegen_arm.h 36 OpSize size, VolatileKind is_volatile) OVERRIDE;
38 OpSize size) OVERRIDE;
42 OpSize size, VolatileKind is_volatile) OVERRIDE;
44 OpSize size) OVERRIDE;
84 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
91 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
93 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
109 bool GenInlinedPeek(CallInfo* info, OpSize size);
110 bool GenInlinedPoke(CallInfo* info, OpSize size);
164 LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size)
    [all...]
utility_arm.cc 693 int scale, OpSize size) {
759 int scale, OpSize size) {
855 OpSize size) {
966 OpSize size, VolatileKind is_volatile) {
996 OpSize size) {
    [all...]
  /art/compiler/dex/quick/mips/
codegen_mips.h 36 OpSize size, VolatileKind is_volatile) OVERRIDE;
38 OpSize size) OVERRIDE;
42 OpSize size, VolatileKind is_volatile) OVERRIDE;
44 OpSize size) OVERRIDE;
84 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
89 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
91 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
107 bool GenInlinedPeek(CallInfo* info, OpSize size);
108 bool GenInlinedPoke(CallInfo* info, OpSize size);
163 OpSize size)
    [all...]
utility_mips.cc 357 int scale, OpSize size) {
410 int scale, OpSize size) {
456 OpSize size) {
553 OpSize size, VolatileKind is_volatile) {
575 RegStorage r_src, OpSize size) {
656 OpSize size, VolatileKind is_volatile) {
int_mips.cc 296 bool MipsMir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) {
312 bool MipsMir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) {
485 void MipsMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
554 void MipsMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
  /art/compiler/dex/quick/arm64/
codegen_arm64.h 76 OpSize size, VolatileKind is_volatile) OVERRIDE;
80 OpSize size) OVERRIDE;
85 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,
90 OpSize size) OVERRIDE;
137 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
144 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
146 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
157 bool GenInlinedReverseBits(CallInfo* info, OpSize size) OVERRIDE;
168 bool GenInlinedPeek(CallInfo* info, OpSize size) OVERRIDE;
169 bool GenInlinedPoke(CallInfo* info, OpSize size) OVERRIDE
    [all...]
utility_arm64.cc     [all...]
  /art/compiler/dex/quick/x86/
target_x86.cc 698 OpSize size = cu_->target64 ? k64 : k32;
715 OpSize size = cu_->target64 ? k64 : k32;
759 RegisterClass X86Mir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) {
1880 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); local
1910 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); local
1941 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); local
2021 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); local
2049 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); local
2074 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); local
2143 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); local
2236 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); local
2277 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); local
    [all...]
codegen_x86.h 73 OpSize size, VolatileKind is_volatile) OVERRIDE;
75 OpSize size) OVERRIDE;
79 OpSize size, VolatileKind is_volatile) OVERRIDE;
81 OpSize size) OVERRIDE;
143 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
146 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
148 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
165 bool GenInlinedPeek(CallInfo* info, OpSize size) OVERRIDE;
166 bool GenInlinedPoke(CallInfo* info, OpSize size) OVERRIDE;
411 RegStorage r_dest, OpSize size)
    [all...]
utility_x86.cc 635 int displacement, RegStorage r_dest, OpSize size) {
762 int scale, OpSize size) {
767 OpSize size, VolatileKind is_volatile) {
782 int displacement, RegStorage r_src, OpSize size) {
866 int scale, OpSize size) {
870 LIR* X86Mir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,
    [all...]
  /external/llvm/test/MC/Disassembler/X86/
prefixes.txt 47 # Test that immediate is printed correctly within opsize prefix
  /external/llvm/test/CodeGen/X86/
rotate4.ll 4 ; a << (b & (OpSize-1)) | a >> ((0 - b) & (OpSize-1))
  /external/chromium_org/third_party/skia/src/core/
SkPictureRecord.cpp 71 static inline size_t getPaintOffset(DrawType op, size_t opSize) {
127 if (0 != (opSize & ~MASK_24) || opSize == MASK_24) {
137 if (kSaveLayerNoBoundsSize == opSize) {
140 SkASSERT(kSaveLayerWithBoundsSize == opSize);
491 uint32_t opSize;
492 DrawType op = peek_op_and_size(writer, offset, &opSize);
498 SkASSERT(kSaveSize == opSize);
504 offset += opSize;
506 op = peek_op_and_size(writer, offset, &opSize);
    [all...]
  /external/chromium_org/third_party/boringssl/src/crypto/perlasm/
x86gas.pl 16 sub opsize() subroutine
42 if ($dst =~ m/^%/o) { $suffix=&opsize($dst); }
43 elsif ($src =~ m/^%/o) { $suffix=&opsize($src); }
  /external/openssl/crypto/perlasm/
x86gas.pl 16 sub opsize() subroutine
42 if ($dst =~ m/^%/o) { $suffix=&opsize($dst); }
43 elsif ($src =~ m/^%/o) { $suffix=&opsize($src); }
  /frameworks/base/tools/obbtool/
Main.cpp 252 if (strncmp(op, name, opsize)) { \
260 const int opsize = strlen(op); local
  /art/compiler/dex/quick/
mir_to_lir.h 592 RegisterClass RegClassBySize(OpSize size) {
    [all...]
dex_file_method_inliner.cc 443 return backend->GenInlinedReverseBytes(info, static_cast<OpSize>(intrinsic.d.data));
445 return backend->GenInlinedReverseBits(info, static_cast<OpSize>(intrinsic.d.data));
488 return backend->GenInlinedPeek(info, static_cast<OpSize>(intrinsic.d.data));
490 return backend->GenInlinedPoke(info, static_cast<OpSize>(intrinsic.d.data));
    [all...]
  /external/skia/src/core/
SkPictureRecord.cpp 79 static inline size_t getPaintOffset(DrawType op, size_t opSize) {
132 if (0 != (opSize & ~MASK_24) || opSize == MASK_24) {
142 if (kSaveLayerNoBoundsSize == opSize) {
145 SkASSERT(kSaveLayerWithBoundsSize == opSize);
511 uint32_t opSize;
512 DrawType op = peek_op_and_size(writer, offset, &opSize);
518 SkASSERT(kSaveSize == opSize);
520 // get the save flag (last 4-bytes of the space allocated for the opSize)
533 offset += opSize;
    [all...]
  /art/compiler/dex/
compiler_enums.h 126 // It is encoded as OpSize << 16 | (number of bits in vector)
262 enum OpSize {
275 std::ostream& operator<<(std::ostream& os, const OpSize& kind);
  /art/runtime/quick/
inline_method_analyser.h 111 // doesn't know the OpSize enumeration.

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