1 /*===---- cpuid.h - X86 cpu model detection --------------------------------=== 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a copy 4 * of this software and associated documentation files (the "Software"), to deal 5 * in the Software without restriction, including without limitation the rights 6 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 * copies of the Software, and to permit persons to whom the Software is 8 * furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 * THE SOFTWARE. 20 * 21 *===-----------------------------------------------------------------------=== 22 */ 23 24 #if !(__x86_64__ || __i386__) 25 #error this header is for x86 only 26 #endif 27 28 /* Features in %ecx for level 1 */ 29 #define bit_SSE3 0x00000001 30 #define bit_PCLMULQDQ 0x00000002 31 #define bit_DTES64 0x00000004 32 #define bit_MONITOR 0x00000008 33 #define bit_DSCPL 0x00000010 34 #define bit_VMX 0x00000020 35 #define bit_SMX 0x00000040 36 #define bit_EIST 0x00000080 37 #define bit_TM2 0x00000100 38 #define bit_SSSE3 0x00000200 39 #define bit_CNXTID 0x00000400 40 #define bit_FMA 0x00001000 41 #define bit_CMPXCHG16B 0x00002000 42 #define bit_xTPR 0x00004000 43 #define bit_PDCM 0x00008000 44 #define bit_PCID 0x00020000 45 #define bit_DCA 0x00040000 46 #define bit_SSE41 0x00080000 47 #define bit_SSE42 0x00100000 48 #define bit_x2APIC 0x00200000 49 #define bit_MOVBE 0x00400000 50 #define bit_POPCNT 0x00800000 51 #define bit_TSCDeadline 0x01000000 52 #define bit_AESNI 0x02000000 53 #define bit_XSAVE 0x04000000 54 #define bit_OSXSAVE 0x08000000 55 #define bit_AVX 0x10000000 56 #define bit_RDRAND 0x40000000 57 58 /* Features in %edx for level 1 */ 59 #define bit_FPU 0x00000001 60 #define bit_VME 0x00000002 61 #define bit_DE 0x00000004 62 #define bit_PSE 0x00000008 63 #define bit_TSC 0x00000010 64 #define bit_MSR 0x00000020 65 #define bit_PAE 0x00000040 66 #define bit_MCE 0x00000080 67 #define bit_CX8 0x00000100 68 #define bit_APIC 0x00000200 69 #define bit_SEP 0x00000800 70 #define bit_MTRR 0x00001000 71 #define bit_PGE 0x00002000 72 #define bit_MCA 0x00004000 73 #define bit_CMOV 0x00008000 74 #define bit_PAT 0x00010000 75 #define bit_PSE36 0x00020000 76 #define bit_PSN 0x00040000 77 #define bit_CLFSH 0x00080000 78 #define bit_DS 0x00200000 79 #define bit_ACPI 0x00400000 80 #define bit_MMX 0x00800000 81 #define bit_FXSR 0x01000000 82 #define bit_FXSAVE bit_FXSR /* for gcc compat */ 83 #define bit_SSE 0x02000000 84 #define bit_SSE2 0x04000000 85 #define bit_SS 0x08000000 86 #define bit_HTT 0x10000000 87 #define bit_TM 0x20000000 88 #define bit_PBE 0x80000000 89 90 /* Features in %ebx for level 7 sub-leaf 0 */ 91 #define bit_FSGSBASE 0x00000001 92 #define bit_SMEP 0x00000080 93 #define bit_ENH_MOVSB 0x00000200 94 95 /* PIC on i386 uses %ebx, so preserve it. */ 96 #if __i386__ 97 #define __cpuid(__level, __eax, __ebx, __ecx, __edx) \ 98 __asm(" pushl %%ebx\n" \ 99 " cpuid\n" \ 100 " mov %%ebx,%1\n" \ 101 " popl %%ebx" \ 102 : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) \ 103 : "0"(__level)) 104 105 #define __cpuid_count(__level, __count, __eax, __ebx, __ecx, __edx) \ 106 __asm(" pushl %%ebx\n" \ 107 " cpuid\n" \ 108 " mov %%ebx,%1\n" \ 109 " popl %%ebx" \ 110 : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) \ 111 : "0"(__level), "2"(__count)) 112 #else 113 #define __cpuid(__level, __eax, __ebx, __ecx, __edx) \ 114 __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \ 115 : "0"(__level)) 116 117 #define __cpuid_count(__level, __count, __eax, __ebx, __ecx, __edx) \ 118 __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \ 119 : "0"(__level), "2"(__count)) 120 #endif 121 122 static __inline int __get_cpuid (unsigned int __level, unsigned int *__eax, 123 unsigned int *__ebx, unsigned int *__ecx, 124 unsigned int *__edx) { 125 __cpuid(__level, *__eax, *__ebx, *__ecx, *__edx); 126 return 1; 127 } 128 129 static __inline int __get_cpuid_max (unsigned int __level, unsigned int *__sig) 130 { 131 unsigned int __eax, __ebx, __ecx, __edx; 132 #if __i386__ 133 int __cpuid_supported; 134 135 __asm(" pushfl\n" 136 " popl %%eax\n" 137 " movl %%eax,%%ecx\n" 138 " xorl $0x00200000,%%eax\n" 139 " pushl %%eax\n" 140 " popfl\n" 141 " pushfl\n" 142 " popl %%eax\n" 143 " movl $0,%0\n" 144 " cmpl %%eax,%%ecx\n" 145 " je 1f\n" 146 " movl $1,%0\n" 147 "1:" 148 : "=r" (__cpuid_supported) : : "eax", "ecx"); 149 if (!__cpuid_supported) 150 return 0; 151 #endif 152 153 __cpuid(__level, __eax, __ebx, __ecx, __edx); 154 if (__sig) 155 *__sig = __ebx; 156 return __eax; 157 } 158
