1 //=- AArch64SchedA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Contains all of the Cortex-A57 specific SchedWriteRes types. The approach 11 // below is to define a generic SchedWriteRes for every combination of 12 // latency and microOps. The naming conventions is to use a prefix, one field 13 // for latency, and one or more microOp count/type designators. 14 // Prefix: A57Write 15 // Latency: #cyc 16 // MicroOp Count/Types: #(B|I|M|L|S|X|W|V) 17 // 18 // e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are 19 // 11 micro-ops to be issued down one I pipe, six S pipes and four V pipes. 20 // 21 //===----------------------------------------------------------------------===// 22 23 //===----------------------------------------------------------------------===// 24 // Define Generic 1 micro-op types 25 26 def A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; } 27 def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; } 28 def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; } 29 def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; } 30 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; } 31 def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18; } 32 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19; } 33 def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; } 34 def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; } 35 def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; } 36 def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2; } 37 def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32; } 38 def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35; } 39 def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; } 40 def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; } 41 def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; } 42 def A57Write_3cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 3; } 43 def A57Write_4cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 4; } 44 def A57Write_4cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 4; } 45 def A57Write_9cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 9; } 46 def A57Write_6cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 6; } 47 def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; } 48 49 50 //===----------------------------------------------------------------------===// 51 // Define Generic 2 micro-op types 52 53 def A57Write_64cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> { 54 let Latency = 64; 55 let NumMicroOps = 2; 56 } 57 def A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI, 58 A57UnitL]> { 59 let Latency = 6; 60 let NumMicroOps = 2; 61 } 62 def A57Write_7cyc_1V_1X : SchedWriteRes<[A57UnitV, 63 A57UnitX]> { 64 let Latency = 7; 65 let NumMicroOps = 2; 66 } 67 def A57Write_8cyc_1L_1V : SchedWriteRes<[A57UnitL, 68 A57UnitV]> { 69 let Latency = 8; 70 let NumMicroOps = 2; 71 } 72 def A57Write_9cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 73 let Latency = 9; 74 let NumMicroOps = 2; 75 } 76 def A57Write_8cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> { 77 let Latency = 8; 78 let NumMicroOps = 2; 79 } 80 def A57Write_6cyc_2L : SchedWriteRes<[A57UnitL, A57UnitL]> { 81 let Latency = 6; 82 let NumMicroOps = 2; 83 } 84 def A57Write_6cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 85 let Latency = 6; 86 let NumMicroOps = 2; 87 } 88 def A57Write_6cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> { 89 let Latency = 6; 90 let NumMicroOps = 2; 91 } 92 def A57Write_5cyc_1I_1L : SchedWriteRes<[A57UnitI, 93 A57UnitL]> { 94 let Latency = 5; 95 let NumMicroOps = 2; 96 } 97 def A57Write_5cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 98 let Latency = 5; 99 let NumMicroOps = 2; 100 } 101 def A57Write_5cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> { 102 let Latency = 5; 103 let NumMicroOps = 2; 104 } 105 def A57Write_10cyc_1L_1V : SchedWriteRes<[A57UnitL, 106 A57UnitV]> { 107 let Latency = 10; 108 let NumMicroOps = 2; 109 } 110 def A57Write_10cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 111 let Latency = 10; 112 let NumMicroOps = 2; 113 } 114 def A57Write_1cyc_1B_1I : SchedWriteRes<[A57UnitB, 115 A57UnitI]> { 116 let Latency = 1; 117 let NumMicroOps = 2; 118 } 119 def A57Write_1cyc_1I_1S : SchedWriteRes<[A57UnitI, 120 A57UnitS]> { 121 let Latency = 1; 122 let NumMicroOps = 2; 123 } 124 def A57Write_2cyc_1B_1I : SchedWriteRes<[A57UnitB, 125 A57UnitI]> { 126 let Latency = 2; 127 let NumMicroOps = 2; 128 } 129 def A57Write_2cyc_2S : SchedWriteRes<[A57UnitS, A57UnitS]> { 130 let Latency = 2; 131 let NumMicroOps = 2; 132 } 133 def A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 134 let Latency = 2; 135 let NumMicroOps = 2; 136 } 137 def A57Write_36cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> { 138 let Latency = 36; 139 let NumMicroOps = 2; 140 } 141 def A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI, 142 A57UnitM]> { 143 let Latency = 3; 144 let NumMicroOps = 2; 145 } 146 def A57Write_3cyc_1I_1S : SchedWriteRes<[A57UnitI, 147 A57UnitS]> { 148 let Latency = 3; 149 let NumMicroOps = 2; 150 } 151 def A57Write_3cyc_1S_1V : SchedWriteRes<[A57UnitS, 152 A57UnitV]> { 153 let Latency = 3; 154 let NumMicroOps = 2; 155 } 156 def A57Write_4cyc_1I_1L : SchedWriteRes<[A57UnitI, 157 A57UnitL]> { 158 let Latency = 4; 159 let NumMicroOps = 2; 160 } 161 def A57Write_4cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> { 162 let Latency = 4; 163 let NumMicroOps = 2; 164 } 165 166 167 //===----------------------------------------------------------------------===// 168 // Define Generic 3 micro-op types 169 170 def A57Write_10cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> { 171 let Latency = 10; 172 let NumMicroOps = 3; 173 } 174 def A57Write_2cyc_1I_2S : SchedWriteRes<[A57UnitI, 175 A57UnitS, A57UnitS]> { 176 let Latency = 2; 177 let NumMicroOps = 3; 178 } 179 def A57Write_3cyc_1I_1S_1V : SchedWriteRes<[A57UnitI, 180 A57UnitS, 181 A57UnitV]> { 182 let Latency = 3; 183 let NumMicroOps = 3; 184 } 185 def A57Write_3cyc_1M_2S : SchedWriteRes<[A57UnitM, 186 A57UnitS, A57UnitS]> { 187 let Latency = 3; 188 let NumMicroOps = 3; 189 } 190 def A57Write_3cyc_3S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS]> { 191 let Latency = 3; 192 let NumMicroOps = 3; 193 } 194 def A57Write_3cyc_2S_1V : SchedWriteRes<[A57UnitS, A57UnitS, 195 A57UnitV]> { 196 let Latency = 3; 197 let NumMicroOps = 3; 198 } 199 def A57Write_5cyc_1I_2L : SchedWriteRes<[A57UnitI, 200 A57UnitL, A57UnitL]> { 201 let Latency = 5; 202 let NumMicroOps = 3; 203 } 204 def A57Write_6cyc_1I_2L : SchedWriteRes<[A57UnitI, 205 A57UnitL, A57UnitL]> { 206 let Latency = 6; 207 let NumMicroOps = 3; 208 } 209 def A57Write_6cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> { 210 let Latency = 6; 211 let NumMicroOps = 3; 212 } 213 def A57Write_7cyc_3L : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL]> { 214 let Latency = 7; 215 let NumMicroOps = 3; 216 } 217 def A57Write_8cyc_1I_1L_1V : SchedWriteRes<[A57UnitI, 218 A57UnitL, 219 A57UnitV]> { 220 let Latency = 8; 221 let NumMicroOps = 3; 222 } 223 def A57Write_8cyc_1L_2V : SchedWriteRes<[A57UnitL, 224 A57UnitV, A57UnitV]> { 225 let Latency = 8; 226 let NumMicroOps = 3; 227 } 228 def A57Write_8cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> { 229 let Latency = 8; 230 let NumMicroOps = 3; 231 } 232 def A57Write_9cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> { 233 let Latency = 9; 234 let NumMicroOps = 3; 235 } 236 237 238 //===----------------------------------------------------------------------===// 239 // Define Generic 4 micro-op types 240 241 def A57Write_2cyc_2I_2S : SchedWriteRes<[A57UnitI, A57UnitI, 242 A57UnitS, A57UnitS]> { 243 let Latency = 2; 244 let NumMicroOps = 4; 245 } 246 def A57Write_3cyc_2I_2S : SchedWriteRes<[A57UnitI, A57UnitI, 247 A57UnitS, A57UnitS]> { 248 let Latency = 3; 249 let NumMicroOps = 4; 250 } 251 def A57Write_3cyc_1I_3S : SchedWriteRes<[A57UnitI, 252 A57UnitS, A57UnitS, A57UnitS]> { 253 let Latency = 3; 254 let NumMicroOps = 4; 255 } 256 def A57Write_3cyc_1I_2S_1V : SchedWriteRes<[A57UnitI, 257 A57UnitS, A57UnitS, 258 A57UnitV]> { 259 let Latency = 3; 260 let NumMicroOps = 4; 261 } 262 def A57Write_4cyc_4S : SchedWriteRes<[A57UnitS, A57UnitS, 263 A57UnitS, A57UnitS]> { 264 let Latency = 4; 265 let NumMicroOps = 4; 266 } 267 def A57Write_7cyc_1I_3L : SchedWriteRes<[A57UnitI, 268 A57UnitL, A57UnitL, A57UnitL]> { 269 let Latency = 7; 270 let NumMicroOps = 4; 271 } 272 def A57Write_5cyc_2I_2L : SchedWriteRes<[A57UnitI, A57UnitI, 273 A57UnitL, A57UnitL]> { 274 let Latency = 5; 275 let NumMicroOps = 4; 276 } 277 def A57Write_8cyc_1I_1L_2V : SchedWriteRes<[A57UnitI, 278 A57UnitL, 279 A57UnitV, A57UnitV]> { 280 let Latency = 8; 281 let NumMicroOps = 4; 282 } 283 def A57Write_8cyc_4L : SchedWriteRes<[A57UnitL, A57UnitL, 284 A57UnitL, A57UnitL]> { 285 let Latency = 8; 286 let NumMicroOps = 4; 287 } 288 def A57Write_9cyc_2L_2V : SchedWriteRes<[A57UnitL, A57UnitL, 289 A57UnitV, A57UnitV]> { 290 let Latency = 9; 291 let NumMicroOps = 4; 292 } 293 def A57Write_9cyc_1L_3V : SchedWriteRes<[A57UnitL, 294 A57UnitV, A57UnitV, A57UnitV]> { 295 let Latency = 9; 296 let NumMicroOps = 4; 297 } 298 299 300 //===----------------------------------------------------------------------===// 301 // Define Generic 5 micro-op types 302 303 def A57Write_3cyc_3S_2V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, 304 A57UnitV, A57UnitV]> { 305 let Latency = 3; 306 let NumMicroOps = 5; 307 } 308 def A57Write_8cyc_1I_4L : SchedWriteRes<[A57UnitI, 309 A57UnitL, A57UnitL, 310 A57UnitL, A57UnitL]> { 311 let Latency = 8; 312 let NumMicroOps = 5; 313 } 314 def A57Write_4cyc_1I_4S : SchedWriteRes<[A57UnitI, 315 A57UnitS, A57UnitS, 316 A57UnitS, A57UnitS]> { 317 let Latency = 4; 318 let NumMicroOps = 5; 319 } 320 def A57Write_9cyc_1I_2L_2V : SchedWriteRes<[A57UnitI, 321 A57UnitL, A57UnitL, 322 A57UnitV, A57UnitV]> { 323 let Latency = 9; 324 let NumMicroOps = 5; 325 } 326 def A57Write_9cyc_1I_1L_3V : SchedWriteRes<[A57UnitI, 327 A57UnitL, 328 A57UnitV, A57UnitV, A57UnitV]> { 329 let Latency = 9; 330 let NumMicroOps = 5; 331 } 332 def A57Write_9cyc_2L_3V : SchedWriteRes<[A57UnitL, A57UnitL, 333 A57UnitV, A57UnitV, A57UnitV]> { 334 let Latency = 9; 335 let NumMicroOps = 5; 336 } 337 338 339 //===----------------------------------------------------------------------===// 340 // Define Generic 6 micro-op types 341 342 def A57Write_3cyc_1I_3S_2V : SchedWriteRes<[A57UnitI, 343 A57UnitS, A57UnitS, A57UnitS, 344 A57UnitV, A57UnitV]> { 345 let Latency = 3; 346 let NumMicroOps = 6; 347 } 348 def A57Write_4cyc_2I_4S : SchedWriteRes<[A57UnitI, A57UnitI, 349 A57UnitS, A57UnitS, 350 A57UnitS, A57UnitS]> { 351 let Latency = 4; 352 let NumMicroOps = 6; 353 } 354 def A57Write_4cyc_4S_2V : SchedWriteRes<[A57UnitS, A57UnitS, 355 A57UnitS, A57UnitS, 356 A57UnitV, A57UnitV]> { 357 let Latency = 4; 358 let NumMicroOps = 6; 359 } 360 def A57Write_6cyc_6S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, 361 A57UnitS, A57UnitS, A57UnitS]> { 362 let Latency = 6; 363 let NumMicroOps = 6; 364 } 365 def A57Write_9cyc_1I_2L_3V : SchedWriteRes<[A57UnitI, 366 A57UnitL, A57UnitL, 367 A57UnitV, A57UnitV, A57UnitV]> { 368 let Latency = 9; 369 let NumMicroOps = 6; 370 } 371 def A57Write_9cyc_1I_1L_4V : SchedWriteRes<[A57UnitI, 372 A57UnitL, 373 A57UnitV, A57UnitV, 374 A57UnitV, A57UnitV]> { 375 let Latency = 9; 376 let NumMicroOps = 6; 377 } 378 def A57Write_9cyc_2L_4V : SchedWriteRes<[A57UnitL, A57UnitL, 379 A57UnitV, A57UnitV, 380 A57UnitV, A57UnitV]> { 381 let Latency = 9; 382 let NumMicroOps = 6; 383 } 384 385 386 //===----------------------------------------------------------------------===// 387 // Define Generic 7 micro-op types 388 389 def A57Write_10cyc_3L_4V : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL, 390 A57UnitV, A57UnitV, 391 A57UnitV, A57UnitV]> { 392 let Latency = 10; 393 let NumMicroOps = 7; 394 } 395 def A57Write_4cyc_1I_4S_2V : SchedWriteRes<[A57UnitI, 396 A57UnitS, A57UnitS, 397 A57UnitS, A57UnitS, 398 A57UnitV, A57UnitV]> { 399 let Latency = 4; 400 let NumMicroOps = 7; 401 } 402 def A57Write_6cyc_1I_6S : SchedWriteRes<[A57UnitI, 403 A57UnitS, A57UnitS, A57UnitS, 404 A57UnitS, A57UnitS, A57UnitS]> { 405 let Latency = 6; 406 let NumMicroOps = 7; 407 } 408 def A57Write_9cyc_1I_2L_4V : SchedWriteRes<[A57UnitI, 409 A57UnitL, A57UnitL, 410 A57UnitV, A57UnitV, 411 A57UnitV, A57UnitV]> { 412 let Latency = 9; 413 let NumMicroOps = 7; 414 } 415 416 417 //===----------------------------------------------------------------------===// 418 // Define Generic 8 micro-op types 419 420 def A57Write_10cyc_1I_3L_4V : SchedWriteRes<[A57UnitI, 421 A57UnitL, A57UnitL, A57UnitL, 422 A57UnitV, A57UnitV, 423 A57UnitV, A57UnitV]> { 424 let Latency = 10; 425 let NumMicroOps = 8; 426 } 427 def A57Write_11cyc_4L_4V : SchedWriteRes<[A57UnitL, A57UnitL, 428 A57UnitL, A57UnitL, 429 A57UnitV, A57UnitV, 430 A57UnitV, A57UnitV]> { 431 let Latency = 11; 432 let NumMicroOps = 8; 433 } 434 def A57Write_8cyc_8S : SchedWriteRes<[A57UnitS, A57UnitS, 435 A57UnitS, A57UnitS, 436 A57UnitS, A57UnitS, 437 A57UnitS, A57UnitS]> { 438 let Latency = 8; 439 let NumMicroOps = 8; 440 } 441 442 443 //===----------------------------------------------------------------------===// 444 // Define Generic 9 micro-op types 445 446 def A57Write_8cyc_1I_8S : SchedWriteRes<[A57UnitI, 447 A57UnitS, A57UnitS, 448 A57UnitS, A57UnitS, 449 A57UnitS, A57UnitS, 450 A57UnitS, A57UnitS]> { 451 let Latency = 8; 452 let NumMicroOps = 9; 453 } 454 def A57Write_11cyc_1I_4L_4V : SchedWriteRes<[A57UnitI, 455 A57UnitL, A57UnitL, 456 A57UnitL, A57UnitL, 457 A57UnitV, A57UnitV, 458 A57UnitV, A57UnitV]> { 459 let Latency = 11; 460 let NumMicroOps = 9; 461 } 462 463 464 //===----------------------------------------------------------------------===// 465 // Define Generic 10 micro-op types 466 467 def A57Write_6cyc_6S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, 468 A57UnitS, A57UnitS, A57UnitS, 469 A57UnitV, A57UnitV, 470 A57UnitV, A57UnitV]> { 471 let Latency = 6; 472 let NumMicroOps = 10; 473 } 474 475 476 //===----------------------------------------------------------------------===// 477 // Define Generic 11 micro-op types 478 479 def A57Write_6cyc_1I_6S_4V : SchedWriteRes<[A57UnitI, 480 A57UnitS, A57UnitS, A57UnitS, 481 A57UnitS, A57UnitS, A57UnitS, 482 A57UnitV, A57UnitV, 483 A57UnitV, A57UnitV]> { 484 let Latency = 6; 485 let NumMicroOps = 11; 486 } 487 488 489 //===----------------------------------------------------------------------===// 490 // Define Generic 12 micro-op types 491 492 def A57Write_8cyc_8S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, A57UnitS, 493 A57UnitS, A57UnitS, A57UnitS, A57UnitS, 494 A57UnitV, A57UnitV, 495 A57UnitV, A57UnitV]> { 496 let Latency = 8; 497 let NumMicroOps = 12; 498 } 499 500 //===----------------------------------------------------------------------===// 501 // Define Generic 13 micro-op types 502 503 def A57Write_8cyc_1I_8S_4V : SchedWriteRes<[A57UnitI, 504 A57UnitS, A57UnitS, A57UnitS, 505 A57UnitS, A57UnitS, A57UnitS, 506 A57UnitS, A57UnitS, 507 A57UnitV, A57UnitV, 508 A57UnitV, A57UnitV]> { 509 let Latency = 8; 510 let NumMicroOps = 13; 511 } 512 513
