1 //===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides ARM specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef ARMMCTARGETDESC_H 15 #define ARMMCTARGETDESC_H 16 17 #include "llvm/Support/DataTypes.h" 18 #include <string> 19 20 namespace llvm { 21 class formatted_raw_ostream; 22 class MCAsmBackend; 23 class MCCodeEmitter; 24 class MCContext; 25 class MCInstrInfo; 26 class MCInstPrinter; 27 class MCObjectWriter; 28 class MCRegisterInfo; 29 class MCSubtargetInfo; 30 class MCStreamer; 31 class MCRelocationInfo; 32 class StringRef; 33 class Target; 34 class raw_ostream; 35 36 extern Target TheARMLETarget, TheThumbLETarget; 37 extern Target TheARMBETarget, TheThumbBETarget; 38 39 namespace ARM_MC { 40 std::string ParseARMTriple(StringRef TT, StringRef CPU); 41 42 /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance. 43 /// This is exposed so Asm parser, etc. do not need to go through 44 /// TargetRegistry. 45 MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, 46 StringRef FS); 47 } 48 49 MCStreamer *createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS, 50 bool isVerboseAsm, bool useDwarfDirectory, 51 MCInstPrinter *InstPrint, MCCodeEmitter *CE, 52 MCAsmBackend *TAB, bool ShowInst); 53 54 MCStreamer *createARMNullStreamer(MCContext &Ctx); 55 56 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII, 57 const MCRegisterInfo &MRI, 58 const MCSubtargetInfo &STI, 59 MCContext &Ctx); 60 61 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII, 62 const MCRegisterInfo &MRI, 63 const MCSubtargetInfo &STI, 64 MCContext &Ctx); 65 66 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI, 67 StringRef TT, StringRef CPU, 68 bool IsLittleEndian); 69 70 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, 71 StringRef TT, StringRef CPU); 72 73 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, 74 StringRef TT, StringRef CPU); 75 76 MCAsmBackend *createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, 77 StringRef TT, StringRef CPU); 78 79 MCAsmBackend *createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, 80 StringRef TT, StringRef CPU); 81 82 /// createARMWinCOFFStreamer - Construct a PE/COFF machine code streamer which 83 /// will generate a PE/COFF object file. 84 MCStreamer *createARMWinCOFFStreamer(MCContext &Context, MCAsmBackend &MAB, 85 MCCodeEmitter &Emitter, raw_ostream &OS); 86 87 /// createARMELFObjectWriter - Construct an ELF Mach-O object writer. 88 MCObjectWriter *createARMELFObjectWriter(raw_ostream &OS, 89 uint8_t OSABI, 90 bool IsLittleEndian); 91 92 /// createARMMachObjectWriter - Construct an ARM Mach-O object writer. 93 MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS, 94 bool Is64Bit, 95 uint32_t CPUType, 96 uint32_t CPUSubtype); 97 98 /// createARMWinCOFFObjectWriter - Construct an ARM PE/COFF object writer. 99 MCObjectWriter *createARMWinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit); 100 101 /// createARMMachORelocationInfo - Construct ARM Mach-O relocation info. 102 MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx); 103 } // End llvm namespace 104 105 // Defines symbolic names for ARM registers. This defines a mapping from 106 // register name to register number. 107 // 108 #define GET_REGINFO_ENUM 109 #include "ARMGenRegisterInfo.inc" 110 111 // Defines symbolic names for the ARM instructions. 112 // 113 #define GET_INSTRINFO_ENUM 114 #include "ARMGenInstrInfo.inc" 115 116 #define GET_SUBTARGETINFO_ENUM 117 #include "ARMGenSubtargetInfo.inc" 118 119 #endif 120
