1 //===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> 11 : Instruction { 12 field bits<32> Inst; 13 14 let Namespace = "SP"; 15 let Size = 4; 16 17 bits<2> op; 18 let Inst{31-30} = op; // Top two bits are the 'op' field 19 20 dag OutOperandList = outs; 21 dag InOperandList = ins; 22 let AsmString = asmstr; 23 let Pattern = pattern; 24 25 let DecoderNamespace = "Sparc"; 26 field bits<32> SoftFail = 0; 27 } 28 29 //===----------------------------------------------------------------------===// 30 // Format #2 instruction classes in the Sparc 31 //===----------------------------------------------------------------------===// 32 33 // Format 2 instructions 34 class F2<dag outs, dag ins, string asmstr, list<dag> pattern> 35 : InstSP<outs, ins, asmstr, pattern> { 36 bits<3> op2; 37 bits<22> imm22; 38 let op = 0; // op = 0 39 let Inst{24-22} = op2; 40 let Inst{21-0} = imm22; 41 } 42 43 // Specific F2 classes: SparcV8 manual, page 44 44 // 45 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern> 46 : F2<outs, ins, asmstr, pattern> { 47 bits<5> rd; 48 49 let op2 = op2Val; 50 51 let Inst{29-25} = rd; 52 } 53 54 class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr, 55 list<dag> pattern> : F2<outs, ins, asmstr, pattern> { 56 bits<4> cond; 57 let op2 = op2Val; 58 59 let Inst{29} = annul; 60 let Inst{28-25} = cond; 61 } 62 63 class F2_3<bits<3> op2Val, bit annul, bit pred, 64 dag outs, dag ins, string asmstr, list<dag> pattern> 65 : InstSP<outs, ins, asmstr, pattern> { 66 bits<2> cc; 67 bits<4> cond; 68 bits<19> imm19; 69 70 let op = 0; // op = 0 71 72 let Inst{29} = annul; 73 let Inst{28-25} = cond; 74 let Inst{24-22} = op2Val; 75 let Inst{21-20} = cc; 76 let Inst{19} = pred; 77 let Inst{18-0} = imm19; 78 } 79 80 class F2_4<bits<3> cond, bit annul, bit pred, 81 dag outs, dag ins, string asmstr, list<dag> pattern> 82 : InstSP<outs, ins, asmstr, pattern> { 83 bits<16> imm16; 84 bits<5> rs1; 85 86 let op = 0; // op = 0 87 88 let Inst{29} = annul; 89 let Inst{28} = 0; 90 let Inst{27-25} = cond; 91 let Inst{24-22} = 0b011; 92 let Inst{21-20} = imm16{15-14}; 93 let Inst{19} = pred; 94 let Inst{18-14} = rs1; 95 let Inst{13-0} = imm16{13-0}; 96 } 97 98 99 //===----------------------------------------------------------------------===// 100 // Format #3 instruction classes in the Sparc 101 //===----------------------------------------------------------------------===// 102 103 class F3<dag outs, dag ins, string asmstr, list<dag> pattern> 104 : InstSP<outs, ins, asmstr, pattern> { 105 bits<5> rd; 106 bits<6> op3; 107 bits<5> rs1; 108 let op{1} = 1; // Op = 2 or 3 109 let Inst{29-25} = rd; 110 let Inst{24-19} = op3; 111 let Inst{18-14} = rs1; 112 } 113 114 // Specific F3 classes: SparcV8 manual, page 44 115 // 116 class F3_1_asi<bits<2> opVal, bits<6> op3val, bits<8> asi, dag outs, dag ins, 117 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 118 bits<5> rs2; 119 120 let op = opVal; 121 let op3 = op3val; 122 123 let Inst{13} = 0; // i field = 0 124 let Inst{12-5} = asi; // address space identifier 125 let Inst{4-0} = rs2; 126 } 127 128 class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr, 129 list<dag> pattern> : F3_1_asi<opVal, op3val, 0, outs, ins, 130 asmstr, pattern>; 131 132 class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 133 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 134 bits<13> simm13; 135 136 let op = opVal; 137 let op3 = op3val; 138 139 let Inst{13} = 1; // i field = 1 140 let Inst{12-0} = simm13; 141 } 142 143 // floating-point 144 class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 145 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 146 bits<5> rs2; 147 148 let op = opVal; 149 let op3 = op3val; 150 151 let Inst{13-5} = opfval; // fp opcode 152 let Inst{4-0} = rs2; 153 } 154 155 // floating-point unary operations. 156 class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 157 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 158 bits<5> rs2; 159 160 let op = opVal; 161 let op3 = op3val; 162 let rs1 = 0; 163 164 let Inst{13-5} = opfval; // fp opcode 165 let Inst{4-0} = rs2; 166 } 167 168 // floating-point compares. 169 class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 170 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 171 bits<5> rs2; 172 173 let op = opVal; 174 let op3 = op3val; 175 176 let Inst{13-5} = opfval; // fp opcode 177 let Inst{4-0} = rs2; 178 } 179 180 // Shift by register rs2. 181 class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, 182 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 183 bit x = xVal; // 1 for 64-bit shifts. 184 bits<5> rs2; 185 186 let op = opVal; 187 let op3 = op3val; 188 189 let Inst{13} = 0; // i field = 0 190 let Inst{12} = x; // extended registers. 191 let Inst{4-0} = rs2; 192 } 193 194 // Shift by immediate. 195 class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, 196 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 197 bit x = xVal; // 1 for 64-bit shifts. 198 bits<6> shcnt; // shcnt32 / shcnt64. 199 200 let op = opVal; 201 let op3 = op3val; 202 203 let Inst{13} = 1; // i field = 1 204 let Inst{12} = x; // extended registers. 205 let Inst{5-0} = shcnt; 206 } 207 208 // Define rr and ri shift instructions with patterns. 209 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode, 210 ValueType VT, RegisterClass RC> { 211 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2), 212 !strconcat(OpcStr, " $rs1, $rs2, $rd"), 213 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>; 214 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt), 215 !strconcat(OpcStr, " $rs1, $shcnt, $rd"), 216 [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>; 217 } 218 219 class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern> 220 : InstSP<outs, ins, asmstr, pattern> { 221 bits<5> rd; 222 223 let op = 2; 224 let Inst{29-25} = rd; 225 let Inst{24-19} = op3; 226 } 227 228 229 class F4_1<bits<6> op3, dag outs, dag ins, 230 string asmstr, list<dag> pattern> 231 : F4<op3, outs, ins, asmstr, pattern> { 232 233 bit intcc; 234 bits<2> cc; 235 bits<4> cond; 236 bits<5> rs2; 237 238 let Inst{4-0} = rs2; 239 let Inst{12-11} = cc; 240 let Inst{13} = 0; 241 let Inst{17-14} = cond; 242 let Inst{18} = intcc; 243 244 } 245 246 class F4_2<bits<6> op3, dag outs, dag ins, 247 string asmstr, list<dag> pattern> 248 : F4<op3, outs, ins, asmstr, pattern> { 249 bit intcc; 250 bits<2> cc; 251 bits<4> cond; 252 bits<11> simm11; 253 254 let Inst{10-0} = simm11; 255 let Inst{12-11} = cc; 256 let Inst{13} = 1; 257 let Inst{17-14} = cond; 258 let Inst{18} = intcc; 259 } 260 261 class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins, 262 string asmstr, list<dag> pattern> 263 : F4<op3, outs, ins, asmstr, pattern> { 264 bits<4> cond; 265 bit intcc; 266 bits<2> opf_cc; 267 bits<5> rs2; 268 269 let Inst{18} = 0; 270 let Inst{17-14} = cond; 271 let Inst{13} = intcc; 272 let Inst{12-11} = opf_cc; 273 let Inst{10-5} = opf_low; 274 let Inst{4-0} = rs2; 275 } 276 277 class F4_4r<bits<6> op3, bits<5> opf_low, bits<3> rcond, dag outs, dag ins, 278 string asmstr, list<dag> pattern> 279 : F4<op3, outs, ins, asmstr, pattern> { 280 bits <5> rs1; 281 bits <5> rs2; 282 let Inst{18-14} = rs1; 283 let Inst{13} = 0; // IsImm 284 let Inst{12-10} = rcond; 285 let Inst{9-5} = opf_low; 286 let Inst{4-0} = rs2; 287 } 288 289 290 class F4_4i<bits<6> op3, bits<3> rcond, dag outs, dag ins, 291 string asmstr, list<dag> pattern> 292 : F4<op3, outs, ins, asmstr, pattern> { 293 bits<5> rs1; 294 bits<10> simm10; 295 let Inst{18-14} = rs1; 296 let Inst{13} = 1; // IsImm 297 let Inst{12-10} = rcond; 298 let Inst{9-0} = simm10; 299 } 300 301 302 class TRAPSP<bits<6> op3Val, bit isimm, dag outs, dag ins, string asmstr, 303 list<dag> pattern>: F3<outs, ins, asmstr, pattern> { 304 305 bits<4> cond; 306 bits<2> cc; 307 308 let op = 0b10; 309 let rd{4} = 0; 310 let rd{3-0} = cond; 311 let op3 = op3Val; 312 let Inst{13} = isimm; 313 let Inst{12-11} = cc; 314 315 } 316 317 class TRAPSPrr<bits<6> op3Val, dag outs, dag ins, string asmstr, 318 list<dag> pattern>: TRAPSP<op3Val, 0, outs, ins, asmstr, pattern> { 319 bits<5> rs2; 320 321 let Inst{10-5} = 0; 322 let Inst{4-0} = rs2; 323 } 324 class TRAPSPri<bits<6> op3Val, dag outs, dag ins, string asmstr, 325 list<dag> pattern>: TRAPSP<op3Val, 1, outs, ins, asmstr, pattern> { 326 bits<8> imm; 327 328 let Inst{10-8} = 0; 329 let Inst{7-0} = imm; 330 } 331
