1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s 2 3 define <2 x i32> @c1(<2 x float> %a) nounwind readnone ssp { 4 ; CHECK: c1 5 ; CHECK: fcvtzs.2s v0, v0 6 ; CHECK: ret 7 %vcvt.i = fptosi <2 x float> %a to <2 x i32> 8 ret <2 x i32> %vcvt.i 9 } 10 11 define <2 x i32> @c2(<2 x float> %a) nounwind readnone ssp { 12 ; CHECK: c2 13 ; CHECK: fcvtzu.2s v0, v0 14 ; CHECK: ret 15 %vcvt.i = fptoui <2 x float> %a to <2 x i32> 16 ret <2 x i32> %vcvt.i 17 } 18 19 define <4 x i32> @c3(<4 x float> %a) nounwind readnone ssp { 20 ; CHECK: c3 21 ; CHECK: fcvtzs.4s v0, v0 22 ; CHECK: ret 23 %vcvt.i = fptosi <4 x float> %a to <4 x i32> 24 ret <4 x i32> %vcvt.i 25 } 26 27 define <4 x i32> @c4(<4 x float> %a) nounwind readnone ssp { 28 ; CHECK: c4 29 ; CHECK: fcvtzu.4s v0, v0 30 ; CHECK: ret 31 %vcvt.i = fptoui <4 x float> %a to <4 x i32> 32 ret <4 x i32> %vcvt.i 33 } 34 35
