1 ; Test an i64 0/-1 SELECTCCC for every floating-point condition. 2 ; 3 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s 4 5 ; Test CC in { 0 } 6 define i64 @f1(float %a, float %b) { 7 ; CHECK-LABEL: f1: 8 ; CHECK: ipm [[REG:%r[0-5]]] 9 ; CHECK-NEXT: afi [[REG]], -268435456 10 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32 11 ; CHECK-NEXT: srag %r2, [[REG]], 63 12 ; CHECK: br %r14 13 %cond = fcmp oeq float %a, %b 14 %res = select i1 %cond, i64 -1, i64 0 15 ret i64 %res 16 } 17 18 ; Test CC in { 1 } 19 define i64 @f2(float %a, float %b) { 20 ; CHECK-LABEL: f2: 21 ; CHECK: ipm [[REG:%r[0-5]]] 22 ; CHECK-NEXT: xilf [[REG]], 268435456 23 ; CHECK-NEXT: afi [[REG]], -268435456 24 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32 25 ; CHECK-NEXT: srag %r2, [[REG]], 63 26 ; CHECK: br %r14 27 %cond = fcmp olt float %a, %b 28 %res = select i1 %cond, i64 -1, i64 0 29 ret i64 %res 30 } 31 32 ; Test CC in { 0, 1 } 33 define i64 @f3(float %a, float %b) { 34 ; CHECK-LABEL: f3: 35 ; CHECK: ipm [[REG:%r[0-5]]] 36 ; CHECK-NEXT: afi [[REG]], -536870912 37 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32 38 ; CHECK-NEXT: srag %r2, [[REG]], 63 39 ; CHECK: br %r14 40 %cond = fcmp ole float %a, %b 41 %res = select i1 %cond, i64 -1, i64 0 42 ret i64 %res 43 } 44 45 ; Test CC in { 2 } 46 define i64 @f4(float %a, float %b) { 47 ; CHECK-LABEL: f4: 48 ; CHECK: ipm [[REG:%r[0-5]]] 49 ; CHECK-NEXT: xilf [[REG]], 268435456 50 ; CHECK-NEXT: afi [[REG]], 1342177280 51 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32 52 ; CHECK-NEXT: srag %r2, [[REG]], 63 53 ; CHECK: br %r14 54 %cond = fcmp ogt float %a, %b 55 %res = select i1 %cond, i64 -1, i64 0 56 ret i64 %res 57 } 58 59 ; Test CC in { 0, 2 } 60 define i64 @f5(float %a, float %b) { 61 ; CHECK-LABEL: f5: 62 ; CHECK: ipm [[REG:%r[0-5]]] 63 ; CHECK-NEXT: xilf [[REG]], 4294967295 64 ; CHECK-NEXT: sllg [[REG]], [[REG]], 35 65 ; CHECK-NEXT: srag %r2, [[REG]], 63 66 ; CHECK: br %r14 67 %cond = fcmp oge float %a, %b 68 %res = select i1 %cond, i64 -1, i64 0 69 ret i64 %res 70 } 71 72 ; Test CC in { 1, 2 } 73 define i64 @f6(float %a, float %b) { 74 ; CHECK-LABEL: f6: 75 ; CHECK: ipm [[REG:%r[0-5]]] 76 ; CHECK-NEXT: afi [[REG]], 268435456 77 ; CHECK-NEXT: sllg [[REG]], [[REG]], 34 78 ; CHECK-NEXT: srag %r2, [[REG]], 63 79 ; CHECK: br %r14 80 %cond = fcmp one float %a, %b 81 %res = select i1 %cond, i64 -1, i64 0 82 ret i64 %res 83 } 84 85 ; Test CC in { 0, 1, 2 } 86 define i64 @f7(float %a, float %b) { 87 ; CHECK-LABEL: f7: 88 ; CHECK: ipm [[REG:%r[0-5]]] 89 ; CHECK-NEXT: afi [[REG]], -805306368 90 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32 91 ; CHECK-NEXT: srag %r2, [[REG]], 63 92 ; CHECK: br %r14 93 %cond = fcmp ord float %a, %b 94 %res = select i1 %cond, i64 -1, i64 0 95 ret i64 %res 96 } 97 98 ; Test CC in { 3 } 99 define i64 @f8(float %a, float %b) { 100 ; CHECK-LABEL: f8: 101 ; CHECK: ipm [[REG:%r[0-5]]] 102 ; CHECK-NEXT: afi [[REG]], 1342177280 103 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32 104 ; CHECK-NEXT: srag %r2, [[REG]], 63 105 ; CHECK: br %r14 106 %cond = fcmp uno float %a, %b 107 %res = select i1 %cond, i64 -1, i64 0 108 ret i64 %res 109 } 110 111 ; Test CC in { 0, 3 } 112 define i64 @f9(float %a, float %b) { 113 ; CHECK-LABEL: f9: 114 ; CHECK: ipm [[REG:%r[0-5]]] 115 ; CHECK-NEXT: afi [[REG]], -268435456 116 ; CHECK-NEXT: sllg [[REG]], [[REG]], 34 117 ; CHECK-NEXT: srag %r2, [[REG]], 63 118 ; CHECK: br %r14 119 %cond = fcmp ueq float %a, %b 120 %res = select i1 %cond, i64 -1, i64 0 121 ret i64 %res 122 } 123 124 ; Test CC in { 1, 3 } 125 define i64 @f10(float %a, float %b) { 126 ; CHECK-LABEL: f10: 127 ; CHECK: ipm [[REG:%r[0-5]]] 128 ; CHECK-NEXT: sllg [[REG]], [[REG]], 35 129 ; CHECK-NEXT: srag %r2, [[REG]], 63 130 ; CHECK: br %r14 131 %cond = fcmp ult float %a, %b 132 %res = select i1 %cond, i64 -1, i64 0 133 ret i64 %res 134 } 135 136 ; Test CC in { 0, 1, 3 } 137 define i64 @f11(float %a, float %b) { 138 ; CHECK-LABEL: f11: 139 ; CHECK: ipm [[REG:%r[0-5]]] 140 ; CHECK-NEXT: xilf [[REG]], 268435456 141 ; CHECK-NEXT: afi [[REG]], -805306368 142 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32 143 ; CHECK-NEXT: srag %r2, [[REG]], 63 144 ; CHECK: br %r14 145 %cond = fcmp ule float %a, %b 146 %res = select i1 %cond, i64 -1, i64 0 147 ret i64 %res 148 } 149 150 ; Test CC in { 2, 3 } 151 define i64 @f12(float %a, float %b) { 152 ; CHECK-LABEL: f12: 153 ; CHECK: ipm [[REG:%r[0-5]]] 154 ; CHECK-NEXT: sllg [[REG]], [[REG]], 34 155 ; CHECK-NEXT: srag %r2, [[REG]], 63 156 ; CHECK: br %r14 157 %cond = fcmp ugt float %a, %b 158 %res = select i1 %cond, i64 -1, i64 0 159 ret i64 %res 160 } 161 162 ; Test CC in { 0, 2, 3 } 163 define i64 @f13(float %a, float %b) { 164 ; CHECK-LABEL: f13: 165 ; CHECK: ipm [[REG:%r[0-5]]] 166 ; CHECK-NEXT: xilf [[REG]], 268435456 167 ; CHECK-NEXT: afi [[REG]], 1879048192 168 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32 169 ; CHECK-NEXT: srag %r2, [[REG]], 63 170 ; CHECK: br %r14 171 %cond = fcmp uge float %a, %b 172 %res = select i1 %cond, i64 -1, i64 0 173 ret i64 %res 174 } 175 176 ; Test CC in { 1, 2, 3 } 177 define i64 @f14(float %a, float %b) { 178 ; CHECK-LABEL: f14: 179 ; CHECK: ipm [[REG:%r[0-5]]] 180 ; CHECK-NEXT: afi [[REG]], 1879048192 181 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32 182 ; CHECK-NEXT: srag %r2, [[REG]], 63 183 ; CHECK: br %r14 184 %cond = fcmp une float %a, %b 185 %res = select i1 %cond, i64 -1, i64 0 186 ret i64 %res 187 } 188
