1 ; Test SETCC for every integer condition. The tests here assume that 2 ; RISBLG isn't available. 3 ; 4 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s 5 6 ; Test CC in { 0 }, with 3 don't care. 7 define i32 @f1(i32 %a, i32 %b) { 8 ; CHECK-LABEL: f1: 9 ; CHECK: ipm %r2 10 ; CHECK-NEXT: afi %r2, -268435456 11 ; CHECK-NEXT: srl %r2, 31 12 ; CHECK: br %r14 13 %cond = icmp eq i32 %a, %b 14 %res = zext i1 %cond to i32 15 ret i32 %res 16 } 17 18 ; Test CC in { 1 }, with 3 don't care. 19 define i32 @f2(i32 %a, i32 %b) { 20 ; CHECK-LABEL: f2: 21 ; CHECK: ipm [[REG:%r[0-5]]] 22 ; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 36 23 ; CHECK: br %r14 24 %cond = icmp slt i32 %a, %b 25 %res = zext i1 %cond to i32 26 ret i32 %res 27 } 28 29 ; Test CC in { 0, 1 }, with 3 don't care. 30 define i32 @f3(i32 %a, i32 %b) { 31 ; CHECK-LABEL: f3: 32 ; CHECK: ipm %r2 33 ; CHECK-NEXT: afi %r2, -536870912 34 ; CHECK-NEXT: srl %r2, 31 35 ; CHECK: br %r14 36 %cond = icmp sle i32 %a, %b 37 %res = zext i1 %cond to i32 38 ret i32 %res 39 } 40 41 ; Test CC in { 2 }, with 3 don't care. 42 define i32 @f4(i32 %a, i32 %b) { 43 ; CHECK-LABEL: f4: 44 ; CHECK: ipm [[REG:%r[0-5]]] 45 ; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 35 46 ; CHECK: br %r14 47 %cond = icmp sgt i32 %a, %b 48 %res = zext i1 %cond to i32 49 ret i32 %res 50 } 51 52 ; Test CC in { 0, 2 }, with 3 don't care. 53 define i32 @f5(i32 %a, i32 %b) { 54 ; CHECK-LABEL: f5: 55 ; CHECK: ipm [[REG:%r[0-5]]] 56 ; CHECK-NEXT: xilf [[REG]], 4294967295 57 ; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 36 58 ; CHECK: br %r14 59 %cond = icmp sge i32 %a, %b 60 %res = zext i1 %cond to i32 61 ret i32 %res 62 } 63 64 ; Test CC in { 1, 2 }, with 3 don't care. 65 define i32 @f6(i32 %a, i32 %b) { 66 ; CHECK-LABEL: f6: 67 ; CHECK: ipm %r2 68 ; CHECK-NEXT: afi %r2, 1879048192 69 ; CHECK-NEXT: srl %r2, 31 70 ; CHECK: br %r14 71 %cond = icmp ne i32 %a, %b 72 %res = zext i1 %cond to i32 73 ret i32 %res 74 } 75
