1 /* 2 * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California. 3 * 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * on the rights to use, copy, modify, merge, publish, distribute, sub 10 * license, and/or sell copies of the Software, and to permit persons to whom 11 * the Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 20 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Gareth Hughes <gareth (at) valinux.com> 27 * Keith Whitwell <keith (at) tungstengraphics.com> 28 */ 29 30 #include "main/glheader.h" 31 #include "main/imports.h" 32 #include "main/api_arrayelt.h" 33 34 #include "swrast/swrast.h" 35 #include "vbo/vbo.h" 36 #include "tnl/t_pipeline.h" 37 #include "swrast_setup/swrast_setup.h" 38 39 #include "radeon_context.h" 40 #include "radeon_mipmap_tree.h" 41 #include "radeon_ioctl.h" 42 #include "radeon_state.h" 43 #include "radeon_queryobj.h" 44 45 #include "../r200/r200_reg.h" 46 47 #include "xmlpool.h" 48 49 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in 50 * 1.3 cmdbuffers allow all previous state to be updated as well as 51 * the tcl scalar and vector areas. 52 */ 53 static struct { 54 int start; 55 int len; 56 const char *name; 57 } packet[RADEON_MAX_STATE_PACKETS] = { 58 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"}, 59 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"}, 60 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"}, 61 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"}, 62 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"}, 63 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"}, 64 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"}, 65 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"}, 66 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"}, 67 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"}, 68 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"}, 69 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"}, 70 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"}, 71 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"}, 72 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"}, 73 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"}, 74 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"}, 75 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"}, 76 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"}, 77 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"}, 78 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17, 79 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"}, 80 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"}, 81 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"}, 82 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"}, 83 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"}, 84 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"}, 85 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"}, 86 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"}, 87 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"}, 88 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"}, 89 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"}, 90 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"}, 91 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"}, 92 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"}, 93 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"}, 94 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"}, 95 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"}, 96 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"}, 97 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"}, 98 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"}, 99 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"}, 100 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"}, 101 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"}, 102 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"}, 103 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"}, 104 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"}, 105 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"}, 106 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"}, 107 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"}, 108 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, 109 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"}, 110 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"}, 111 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"}, 112 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"}, 113 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"}, 114 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"}, 115 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"}, 116 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"}, 117 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"}, 118 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"}, 119 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"}, 120 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, 121 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"}, 122 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */ 123 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */ 124 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"}, 125 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"}, 126 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"}, 127 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"}, 128 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"}, 129 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"}, 130 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"}, 131 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"}, 132 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"}, 133 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"}, 134 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"}, 135 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"}, 136 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"}, 137 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"}, 138 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"}, 139 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, 140 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, 141 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, 142 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, 143 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, 144 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, 145 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, 146 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */ 147 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"}, 148 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, 149 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, 150 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, 151 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, 152 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, 153 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, 154 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, 155 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"}, 156 }; 157 158 /* ============================================================= 159 * State initialization 160 */ 161 static int cmdpkt( r100ContextPtr rmesa, int id ) 162 { 163 return CP_PACKET0(packet[id].start, packet[id].len - 1); 164 } 165 166 static int cmdvec( int offset, int stride, int count ) 167 { 168 drm_radeon_cmd_header_t h; 169 h.i = 0; 170 h.vectors.cmd_type = RADEON_CMD_VECTORS; 171 h.vectors.offset = offset; 172 h.vectors.stride = stride; 173 h.vectors.count = count; 174 return h.i; 175 } 176 177 static int cmdscl( int offset, int stride, int count ) 178 { 179 drm_radeon_cmd_header_t h; 180 h.i = 0; 181 h.scalars.cmd_type = RADEON_CMD_SCALARS; 182 h.scalars.offset = offset; 183 h.scalars.stride = stride; 184 h.scalars.count = count; 185 return h.i; 186 } 187 188 #define CHECK( NM, FLAG, ADD ) \ 189 static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom ) \ 190 { \ 191 return FLAG ? atom->cmd_size + (ADD) : 0; \ 192 } 193 194 #define TCL_CHECK( NM, FLAG, ADD ) \ 195 static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom ) \ 196 { \ 197 r100ContextPtr rmesa = R100_CONTEXT(ctx); \ 198 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ 199 } 200 201 202 CHECK( always, GL_TRUE, 0 ) 203 CHECK( always_add2, GL_TRUE, 2 ) 204 CHECK( always_add4, GL_TRUE, 4 ) 205 CHECK( tex0_mm, GL_TRUE, 3 ) 206 CHECK( tex1_mm, GL_TRUE, 3 ) 207 /* need this for the cubic_map on disabled unit 2 bug, maybe r100 only? */ 208 CHECK( tex2_mm, GL_TRUE, 3 ) 209 CHECK( cube0_mm, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE ) 210 CHECK( cube1_mm, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE ) 211 CHECK( cube2_mm, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE ) 212 CHECK( fog_add4, ctx->Fog.Enabled, 4 ) 213 TCL_CHECK( tcl_add4, GL_TRUE, 4 ) 214 TCL_CHECK( tcl_tex0_add4, ctx->Texture.Unit[0]._ReallyEnabled, 4 ) 215 TCL_CHECK( tcl_tex1_add4, ctx->Texture.Unit[1]._ReallyEnabled, 4 ) 216 TCL_CHECK( tcl_tex2_add4, ctx->Texture.Unit[2]._ReallyEnabled, 4 ) 217 TCL_CHECK( tcl_lighting, ctx->Light.Enabled, 0 ) 218 TCL_CHECK( tcl_lighting_add4, ctx->Light.Enabled, 4 ) 219 TCL_CHECK( tcl_eyespace_or_lighting_add4, ctx->_NeedEyeCoords || ctx->Light.Enabled, 4 ) 220 TCL_CHECK( tcl_lit0_add6, ctx->Light.Enabled && ctx->Light.Light[0].Enabled, 6 ) 221 TCL_CHECK( tcl_lit1_add6, ctx->Light.Enabled && ctx->Light.Light[1].Enabled, 6 ) 222 TCL_CHECK( tcl_lit2_add6, ctx->Light.Enabled && ctx->Light.Light[2].Enabled, 6 ) 223 TCL_CHECK( tcl_lit3_add6, ctx->Light.Enabled && ctx->Light.Light[3].Enabled, 6 ) 224 TCL_CHECK( tcl_lit4_add6, ctx->Light.Enabled && ctx->Light.Light[4].Enabled, 6 ) 225 TCL_CHECK( tcl_lit5_add6, ctx->Light.Enabled && ctx->Light.Light[5].Enabled, 6 ) 226 TCL_CHECK( tcl_lit6_add6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled, 6 ) 227 TCL_CHECK( tcl_lit7_add6, ctx->Light.Enabled && ctx->Light.Light[7].Enabled, 6 ) 228 TCL_CHECK( tcl_ucp0_add4, (ctx->Transform.ClipPlanesEnabled & 0x1), 4 ) 229 TCL_CHECK( tcl_ucp1_add4, (ctx->Transform.ClipPlanesEnabled & 0x2), 4 ) 230 TCL_CHECK( tcl_ucp2_add4, (ctx->Transform.ClipPlanesEnabled & 0x4), 4 ) 231 TCL_CHECK( tcl_ucp3_add4, (ctx->Transform.ClipPlanesEnabled & 0x8), 4 ) 232 TCL_CHECK( tcl_ucp4_add4, (ctx->Transform.ClipPlanesEnabled & 0x10), 4 ) 233 TCL_CHECK( tcl_ucp5_add4, (ctx->Transform.ClipPlanesEnabled & 0x20), 4 ) 234 TCL_CHECK( tcl_eyespace_or_fog_add4, ctx->_NeedEyeCoords || ctx->Fog.Enabled, 4 ) 235 236 CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT), 0 ) 237 CHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT), 0 ) 238 CHECK( txr2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT), 0 ) 239 240 #define OUT_VEC(hdr, data) do { \ 241 drm_radeon_cmd_header_t h; \ 242 h.i = hdr; \ 243 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \ 244 OUT_BATCH(0); \ 245 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \ 246 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \ 247 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \ 248 OUT_BATCH_TABLE((data), h.vectors.count); \ 249 } while(0) 250 251 #define OUT_SCL(hdr, data) do { \ 252 drm_radeon_cmd_header_t h; \ 253 h.i = hdr; \ 254 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \ 255 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \ 256 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \ 257 OUT_BATCH_TABLE((data), h.scalars.count); \ 258 } while(0) 259 260 static void scl_emit(struct gl_context *ctx, struct radeon_state_atom *atom) 261 { 262 r100ContextPtr r100 = R100_CONTEXT(ctx); 263 BATCH_LOCALS(&r100->radeon); 264 uint32_t dwords = atom->check(ctx, atom); 265 266 BEGIN_BATCH_NO_AUTOSTATE(dwords); 267 OUT_SCL(atom->cmd[0], atom->cmd+1); 268 END_BATCH(); 269 } 270 271 272 static void vec_emit(struct gl_context *ctx, struct radeon_state_atom *atom) 273 { 274 r100ContextPtr r100 = R100_CONTEXT(ctx); 275 BATCH_LOCALS(&r100->radeon); 276 uint32_t dwords = atom->check(ctx, atom); 277 278 BEGIN_BATCH_NO_AUTOSTATE(dwords); 279 OUT_VEC(atom->cmd[0], atom->cmd+1); 280 END_BATCH(); 281 } 282 283 284 static void lit_emit(struct gl_context *ctx, struct radeon_state_atom *atom) 285 { 286 r100ContextPtr r100 = R100_CONTEXT(ctx); 287 BATCH_LOCALS(&r100->radeon); 288 uint32_t dwords = atom->check(ctx, atom); 289 290 BEGIN_BATCH_NO_AUTOSTATE(dwords); 291 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1); 292 OUT_SCL(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1); 293 END_BATCH(); 294 } 295 296 static int check_always_ctx( struct gl_context *ctx, struct radeon_state_atom *atom) 297 { 298 r100ContextPtr r100 = R100_CONTEXT(ctx); 299 struct radeon_renderbuffer *rrb, *drb; 300 uint32_t dwords; 301 302 rrb = radeon_get_colorbuffer(&r100->radeon); 303 if (!rrb || !rrb->bo) { 304 return 0; 305 } 306 307 drb = radeon_get_depthbuffer(&r100->radeon); 308 309 dwords = 10; 310 if (drb) 311 dwords += 6; 312 if (rrb) 313 dwords += 8; 314 315 return dwords; 316 } 317 318 static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) 319 { 320 r100ContextPtr r100 = R100_CONTEXT(ctx); 321 BATCH_LOCALS(&r100->radeon); 322 struct radeon_renderbuffer *rrb, *drb; 323 uint32_t cbpitch = 0; 324 uint32_t zbpitch = 0; 325 uint32_t dwords = atom->check(ctx, atom); 326 uint32_t depth_fmt; 327 328 rrb = radeon_get_colorbuffer(&r100->radeon); 329 if (!rrb || !rrb->bo) { 330 fprintf(stderr, "no rrb\n"); 331 return; 332 } 333 334 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); 335 if (rrb->cpp == 4) 336 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; 337 else switch (rrb->base.Base.Format) { 338 case MESA_FORMAT_RGB565: 339 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; 340 break; 341 case MESA_FORMAT_ARGB4444: 342 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444; 343 break; 344 case MESA_FORMAT_ARGB1555: 345 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555; 346 break; 347 default: 348 _mesa_problem(ctx, "unexpected format in ctx_emit_cs()"); 349 } 350 351 cbpitch = (rrb->pitch / rrb->cpp); 352 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) 353 cbpitch |= R200_COLOR_TILE_ENABLE; 354 if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) 355 cbpitch |= RADEON_COLOR_MICROTILE_ENABLE; 356 357 drb = radeon_get_depthbuffer(&r100->radeon); 358 if (drb) { 359 zbpitch = (drb->pitch / drb->cpp); 360 if (drb->cpp == 4) 361 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; 362 else 363 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; 364 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK; 365 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; 366 367 } 368 369 BEGIN_BATCH_NO_AUTOSTATE(dwords); 370 371 /* In the CS case we need to split this up */ 372 OUT_BATCH(CP_PACKET0(packet[0].start, 3)); 373 OUT_BATCH_TABLE((atom->cmd + 1), 4); 374 375 if (drb) { 376 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0)); 377 OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); 378 379 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0)); 380 OUT_BATCH(zbpitch); 381 } 382 383 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0)); 384 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); 385 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1)); 386 OUT_BATCH(atom->cmd[CTX_PP_CNTL]); 387 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); 388 389 if (rrb) { 390 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0)); 391 OUT_BATCH_RELOC(rrb->draw_offset, rrb->bo, rrb->draw_offset, 0, RADEON_GEM_DOMAIN_VRAM, 0); 392 393 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); 394 OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0); 395 } 396 397 // if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) { 398 // OUT_BATCH_TABLE((atom->cmd + 14), 4); 399 // } 400 401 END_BATCH(); 402 BEGIN_BATCH_NO_AUTOSTATE(4); 403 OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); 404 OUT_BATCH(0); 405 OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); 406 if (rrb) { 407 OUT_BATCH(((rrb->base.Base.Width - 1) << RADEON_RE_WIDTH_SHIFT) | 408 ((rrb->base.Base.Height - 1) << RADEON_RE_HEIGHT_SHIFT)); 409 } else { 410 OUT_BATCH(0); 411 } 412 END_BATCH(); 413 } 414 415 static void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) 416 { 417 r100ContextPtr r100 = R100_CONTEXT(ctx); 418 BATCH_LOCALS(&r100->radeon); 419 uint32_t dwords = atom->check(ctx, atom); 420 int i = atom->idx, j; 421 radeonTexObj *t = r100->state.texture.unit[i].texobj; 422 radeon_mipmap_level *lvl; 423 uint32_t base_reg; 424 425 if (!(ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) 426 return; 427 428 if (!t) 429 return; 430 431 if (!t->mt) 432 return; 433 434 switch(i) { 435 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break; 436 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break; 437 default: 438 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break; 439 }; 440 BEGIN_BATCH_NO_AUTOSTATE(dwords); 441 OUT_BATCH_TABLE(atom->cmd, 2); 442 lvl = &t->mt->levels[0]; 443 for (j = 0; j < 5; j++) { 444 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0)); 445 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, 446 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 447 } 448 END_BATCH(); 449 } 450 451 static void tex_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) 452 { 453 r100ContextPtr r100 = R100_CONTEXT(ctx); 454 BATCH_LOCALS(&r100->radeon); 455 uint32_t dwords = atom->cmd_size; 456 int i = atom->idx; 457 radeonTexObj *t = r100->state.texture.unit[i].texobj; 458 radeon_mipmap_level *lvl; 459 int hastexture = 1; 460 461 if (!t) 462 hastexture = 0; 463 else { 464 if (!t->mt && !t->bo) 465 hastexture = 0; 466 } 467 dwords += 1; 468 if (hastexture) 469 dwords += 2; 470 else 471 dwords -= 2; 472 BEGIN_BATCH_NO_AUTOSTATE(dwords); 473 474 OUT_BATCH(CP_PACKET0(RADEON_PP_TXFILTER_0 + (24 * i), 1)); 475 OUT_BATCH_TABLE((atom->cmd + 1), 2); 476 477 if (hastexture) { 478 OUT_BATCH(CP_PACKET0(RADEON_PP_TXOFFSET_0 + (24 * i), 0)); 479 if (t->mt && !t->image_override) { 480 if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) { 481 lvl = &t->mt->levels[t->minLod]; 482 OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, 483 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 484 } else { 485 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t), 486 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 487 } 488 } else { 489 if (t->bo) 490 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, 491 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 492 } 493 } 494 495 OUT_BATCH(CP_PACKET0(RADEON_PP_TXCBLEND_0 + (i * 24), 1)); 496 OUT_BATCH_TABLE((atom->cmd+4), 2); 497 OUT_BATCH(CP_PACKET0(RADEON_PP_BORDER_COLOR_0 + (i * 4), 0)); 498 OUT_BATCH((atom->cmd[TEX_PP_BORDER_COLOR])); 499 END_BATCH(); 500 } 501 502 /* Initialize the context's hardware state. 503 */ 504 void radeonInitState( r100ContextPtr rmesa ) 505 { 506 struct gl_context *ctx = rmesa->radeon.glCtx; 507 GLuint i; 508 509 rmesa->radeon.Fallback = 0; 510 511 512 rmesa->radeon.hw.max_state_size = 0; 513 514 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \ 515 do { \ 516 rmesa->hw.ATOM.cmd_size = SZ; \ 517 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ 518 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ 519 rmesa->hw.ATOM.name = NM; \ 520 rmesa->hw.ATOM.is_tcl = FLAG; \ 521 rmesa->hw.ATOM.check = check_##CHK; \ 522 rmesa->hw.ATOM.dirty = GL_TRUE; \ 523 rmesa->hw.ATOM.idx = IDX; \ 524 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \ 525 } while (0) 526 527 #define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \ 528 ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0) 529 530 /* Allocate state buffers: 531 */ 532 ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE, "CTX/context", 0 ); 533 rmesa->hw.ctx.emit = ctx_emit_cs; 534 rmesa->hw.ctx.check = check_always_ctx; 535 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); 536 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); 537 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 ); 538 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 ); 539 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 ); 540 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 ); 541 ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 ); 542 ALLOC_STATE( mtl, tcl_lighting, MTL_STATE_SIZE, "MTL/material", 1 ); 543 ALLOC_STATE( grd, always_add2, GRD_STATE_SIZE, "GRD/guard-band", 1 ); 544 ALLOC_STATE( fog, fog_add4, FOG_STATE_SIZE, "FOG/fog", 1 ); 545 ALLOC_STATE( glt, tcl_lighting_add4, GLT_STATE_SIZE, "GLT/light-global", 1 ); 546 ALLOC_STATE( eye, tcl_lighting_add4, EYE_STATE_SIZE, "EYE/eye-vector", 1 ); 547 ALLOC_STATE_IDX( tex[0], tex0_mm, TEX_STATE_SIZE, "TEX/tex-0", 0, 0); 548 ALLOC_STATE_IDX( tex[1], tex1_mm, TEX_STATE_SIZE, "TEX/tex-1", 0, 1); 549 ALLOC_STATE_IDX( tex[2], tex2_mm, TEX_STATE_SIZE, "TEX/tex-2", 0, 2); 550 ALLOC_STATE( mat[0], tcl_add4, MAT_STATE_SIZE, "MAT/modelproject", 1 ); 551 ALLOC_STATE( mat[1], tcl_eyespace_or_fog_add4, MAT_STATE_SIZE, "MAT/modelview", 1 ); 552 ALLOC_STATE( mat[2], tcl_eyespace_or_lighting_add4, MAT_STATE_SIZE, "MAT/it-modelview", 1 ); 553 ALLOC_STATE( mat[3], tcl_tex0_add4, MAT_STATE_SIZE, "MAT/texmat0", 1 ); 554 ALLOC_STATE( mat[4], tcl_tex1_add4, MAT_STATE_SIZE, "MAT/texmat1", 1 ); 555 ALLOC_STATE( mat[5], tcl_tex2_add4, MAT_STATE_SIZE, "MAT/texmat2", 1 ); 556 ALLOC_STATE( lit[0], tcl_lit0_add6, LIT_STATE_SIZE, "LIT/light-0", 1 ); 557 ALLOC_STATE( lit[1], tcl_lit1_add6, LIT_STATE_SIZE, "LIT/light-1", 1 ); 558 ALLOC_STATE( lit[2], tcl_lit2_add6, LIT_STATE_SIZE, "LIT/light-2", 1 ); 559 ALLOC_STATE( lit[3], tcl_lit3_add6, LIT_STATE_SIZE, "LIT/light-3", 1 ); 560 ALLOC_STATE( lit[4], tcl_lit4_add6, LIT_STATE_SIZE, "LIT/light-4", 1 ); 561 ALLOC_STATE( lit[5], tcl_lit5_add6, LIT_STATE_SIZE, "LIT/light-5", 1 ); 562 ALLOC_STATE( lit[6], tcl_lit6_add6, LIT_STATE_SIZE, "LIT/light-6", 1 ); 563 ALLOC_STATE( lit[7], tcl_lit7_add6, LIT_STATE_SIZE, "LIT/light-7", 1 ); 564 ALLOC_STATE( ucp[0], tcl_ucp0_add4, UCP_STATE_SIZE, "UCP/userclip-0", 1 ); 565 ALLOC_STATE( ucp[1], tcl_ucp1_add4, UCP_STATE_SIZE, "UCP/userclip-1", 1 ); 566 ALLOC_STATE( ucp[2], tcl_ucp2_add4, UCP_STATE_SIZE, "UCP/userclip-2", 1 ); 567 ALLOC_STATE( ucp[3], tcl_ucp3_add4, UCP_STATE_SIZE, "UCP/userclip-3", 1 ); 568 ALLOC_STATE( ucp[4], tcl_ucp4_add4, UCP_STATE_SIZE, "UCP/userclip-4", 1 ); 569 ALLOC_STATE( ucp[5], tcl_ucp5_add4, UCP_STATE_SIZE, "UCP/userclip-5", 1 ); 570 ALLOC_STATE( stp, always, STP_STATE_SIZE, "STP/stp", 0 ); 571 572 for (i = 0; i < 3; i++) { 573 rmesa->hw.tex[i].emit = tex_emit_cs; 574 } 575 ALLOC_STATE_IDX( cube[0], cube0_mm, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); 576 ALLOC_STATE_IDX( cube[1], cube1_mm, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); 577 ALLOC_STATE_IDX( cube[2], cube2_mm, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); 578 for (i = 0; i < 3; i++) 579 rmesa->hw.cube[i].emit = cube_emit_cs; 580 581 ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 ); 582 ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 ); 583 ALLOC_STATE_IDX( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0, 2 ); 584 585 radeonSetUpAtomList( rmesa ); 586 587 /* Fill in the packet headers: 588 */ 589 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC); 590 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL); 591 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH); 592 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN); 593 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH); 594 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK); 595 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE); 596 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL); 597 rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL_STATUS); 598 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC); 599 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_0); 600 rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_0); 601 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_1); 602 rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_1); 603 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_2); 604 rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_2); 605 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_0); 606 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T0); 607 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_1); 608 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T1); 609 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_2); 610 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T2); 611 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR); 612 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT); 613 rmesa->hw.mtl.cmd[MTL_CMD_0] = 614 cmdpkt(rmesa, RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED); 615 rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_0); 616 rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_1); 617 rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_2); 618 rmesa->hw.grd.cmd[GRD_CMD_0] = 619 cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 ); 620 rmesa->hw.fog.cmd[FOG_CMD_0] = 621 cmdvec( RADEON_VS_FOG_PARAM_ADDR, 1, 4 ); 622 rmesa->hw.glt.cmd[GLT_CMD_0] = 623 cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR, 1, 4 ); 624 rmesa->hw.eye.cmd[EYE_CMD_0] = 625 cmdvec( RADEON_VS_EYE_VECTOR_ADDR, 1, 4 ); 626 627 for (i = 0 ; i < 6; i++) { 628 rmesa->hw.mat[i].cmd[MAT_CMD_0] = 629 cmdvec( RADEON_VS_MATRIX_0_ADDR + i*4, 1, 16); 630 } 631 632 for (i = 0 ; i < 8; i++) { 633 rmesa->hw.lit[i].cmd[LIT_CMD_0] = 634 cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 ); 635 rmesa->hw.lit[i].cmd[LIT_CMD_1] = 636 cmdscl( RADEON_SS_LIGHT_DCD_ADDR + i, 8, 6 ); 637 } 638 639 for (i = 0 ; i < 6; i++) { 640 rmesa->hw.ucp[i].cmd[UCP_CMD_0] = 641 cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 ); 642 } 643 644 rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0); 645 rmesa->hw.stp.cmd[STP_DATA_0] = 0; 646 rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31); 647 648 rmesa->hw.grd.emit = scl_emit; 649 rmesa->hw.fog.emit = vec_emit; 650 rmesa->hw.glt.emit = vec_emit; 651 rmesa->hw.eye.emit = vec_emit; 652 for (i = 0; i < 6; i++) 653 rmesa->hw.mat[i].emit = vec_emit; 654 655 for (i = 0; i < 8; i++) 656 rmesa->hw.lit[i].emit = lit_emit; 657 658 for (i = 0; i < 6; i++) 659 rmesa->hw.ucp[i].emit = vec_emit; 660 661 rmesa->last_ReallyEnabled = -1; 662 663 /* Initial Harware state: 664 */ 665 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (RADEON_ALPHA_TEST_PASS | 666 RADEON_CHROMA_FUNC_FAIL | 667 RADEON_CHROMA_KEY_NEAREST | 668 RADEON_SHADOW_FUNC_EQUAL | 669 RADEON_SHADOW_PASS_1 /*| 670 RADEON_RIGHT_HAND_CUBE_OGL */); 671 672 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (RADEON_FOG_VERTEX | 673 /* this bit unused for vertex fog */ 674 RADEON_FOG_USE_DEPTH); 675 676 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000; 677 678 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (RADEON_COMB_FCN_ADD_CLAMP | 679 RADEON_SRC_BLEND_GL_ONE | 680 RADEON_DST_BLEND_GL_ZERO ); 681 682 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (RADEON_Z_TEST_LESS | 683 RADEON_STENCIL_TEST_ALWAYS | 684 RADEON_STENCIL_FAIL_KEEP | 685 RADEON_STENCIL_ZPASS_KEEP | 686 RADEON_STENCIL_ZFAIL_KEEP | 687 RADEON_Z_WRITE_ENABLE); 688 689 if (rmesa->using_hyperz) { 690 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE | 691 RADEON_Z_DECOMPRESSION_ENABLE; 692 if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { 693 /* works for q3, but slight rendering errors with glxgears ? */ 694 /* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/ 695 /* need this otherwise get lots of lockups with q3 ??? */ 696 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY; 697 } 698 } 699 700 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE | 701 RADEON_ANTI_ALIAS_NONE); 702 703 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE | 704 RADEON_ZBLOCK16); 705 706 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) { 707 case DRI_CONF_DITHER_XERRORDIFFRESET: 708 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT; 709 break; 710 case DRI_CONF_DITHER_ORDERED: 711 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE; 712 break; 713 } 714 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) == 715 DRI_CONF_ROUND_ROUND ) 716 rmesa->radeon.state.color.roundEnable = RADEON_ROUND_ENABLE; 717 else 718 rmesa->radeon.state.color.roundEnable = 0; 719 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) == 720 DRI_CONF_COLOR_REDUCTION_DITHER ) 721 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE; 722 else 723 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable; 724 725 726 rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW | 727 RADEON_BFACE_SOLID | 728 RADEON_FFACE_SOLID | 729 /* RADEON_BADVTX_CULL_DISABLE | */ 730 RADEON_FLAT_SHADE_VTX_LAST | 731 RADEON_DIFFUSE_SHADE_GOURAUD | 732 RADEON_ALPHA_SHADE_GOURAUD | 733 RADEON_SPECULAR_SHADE_GOURAUD | 734 RADEON_FOG_SHADE_GOURAUD | 735 RADEON_VPORT_XY_XFORM_ENABLE | 736 RADEON_VPORT_Z_XFORM_ENABLE | 737 RADEON_VTX_PIX_CENTER_OGL | 738 RADEON_ROUND_MODE_TRUNC | 739 RADEON_ROUND_PREC_8TH_PIX); 740 741 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] = 742 #ifdef MESA_BIG_ENDIAN 743 RADEON_VC_32BIT_SWAP; 744 #else 745 RADEON_VC_NO_SWAP; 746 #endif 747 748 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { 749 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS; 750 } 751 752 rmesa->hw.set.cmd[SET_SE_COORDFMT] = ( 753 RADEON_VTX_W0_IS_NOT_1_OVER_W0 | 754 RADEON_TEX1_W_ROUTING_USE_Q1); 755 756 757 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff); 758 759 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] = 760 ((0 << RADEON_LINE_CURRENT_PTR_SHIFT) | 761 (1 << RADEON_LINE_CURRENT_COUNT_SHIFT)); 762 763 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4); 764 765 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] = 766 ((0x00 << RADEON_STENCIL_REF_SHIFT) | 767 (0xff << RADEON_STENCIL_MASK_SHIFT) | 768 (0xff << RADEON_STENCIL_WRITEMASK_SHIFT)); 769 770 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = RADEON_ROP_COPY; 771 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff; 772 773 rmesa->hw.msc.cmd[MSC_RE_MISC] = 774 ((0 << RADEON_STIPPLE_X_OFFSET_SHIFT) | 775 (0 << RADEON_STIPPLE_Y_OFFSET_SHIFT) | 776 RADEON_STIPPLE_BIG_BIT_ORDER); 777 778 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000; 779 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000; 780 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000; 781 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000; 782 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000; 783 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000; 784 785 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) { 786 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL; 787 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] = 788 (RADEON_TXFORMAT_ENDIAN_NO_SWAP | 789 RADEON_TXFORMAT_PERSPECTIVE_ENABLE | 790 (i << 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */ 791 (2 << RADEON_TXFORMAT_WIDTH_SHIFT) | 792 (2 << RADEON_TXFORMAT_HEIGHT_SHIFT)); 793 794 /* Initialize the texture offset to the start of the card texture heap */ 795 // rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] = 796 // rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 797 798 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0; 799 rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] = 800 (RADEON_COLOR_ARG_A_ZERO | 801 RADEON_COLOR_ARG_B_ZERO | 802 RADEON_COLOR_ARG_C_CURRENT_COLOR | 803 RADEON_BLEND_CTL_ADD | 804 RADEON_SCALE_1X | 805 RADEON_CLAMP_TX); 806 rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] = 807 (RADEON_ALPHA_ARG_A_ZERO | 808 RADEON_ALPHA_ARG_B_ZERO | 809 RADEON_ALPHA_ARG_C_CURRENT_ALPHA | 810 RADEON_BLEND_CTL_ADD | 811 RADEON_SCALE_1X | 812 RADEON_CLAMP_TX); 813 rmesa->hw.tex[i].cmd[TEX_PP_TFACTOR] = 0; 814 815 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0; 816 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] = 817 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 818 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_1] = 819 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 820 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_2] = 821 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 822 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_3] = 823 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 824 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_4] = 825 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 826 } 827 828 /* Can only add ST1 at the time of doing some multitex but can keep 829 * it after that. Errors if DIFFUSE is missing. 830 */ 831 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = 832 (RADEON_TCL_VTX_Z0 | 833 RADEON_TCL_VTX_W0 | 834 RADEON_TCL_VTX_PK_DIFFUSE 835 ); /* need to keep this uptodate */ 836 837 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] = 838 ( RADEON_TCL_COMPUTE_XYZW | 839 (RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) | 840 (RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) | 841 (RADEON_TCL_TEX_INPUT_TEX_2 << RADEON_TCL_TEX_2_OUTPUT_SHIFT)); 842 843 844 /* XXX */ 845 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] = 846 ((MODEL << RADEON_MODELVIEW_0_SHIFT) | 847 (MODEL_IT << RADEON_IT_MODELVIEW_0_SHIFT)); 848 849 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] = 850 ((MODEL_PROJ << RADEON_MODELPROJECT_0_SHIFT) | 851 (TEXMAT_0 << RADEON_TEXMAT_0_SHIFT) | 852 (TEXMAT_1 << RADEON_TEXMAT_1_SHIFT) | 853 (TEXMAT_2 << RADEON_TEXMAT_2_SHIFT)); 854 855 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = 856 (RADEON_UCP_IN_CLIP_SPACE | 857 RADEON_CULL_FRONT_IS_CCW); 858 859 rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0; 860 861 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = 862 (RADEON_SPECULAR_LIGHTS | 863 RADEON_DIFFUSE_SPECULAR_COMBINE | 864 RADEON_LOCAL_LIGHT_VEC_GL | 865 (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) | 866 (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) | 867 (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) | 868 (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT)); 869 870 for (i = 0 ; i < 8; i++) { 871 struct gl_light *l = &ctx->Light.Light[i]; 872 GLenum p = GL_LIGHT0 + i; 873 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX; 874 875 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient ); 876 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse ); 877 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular ); 878 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL ); 879 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL ); 880 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent ); 881 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff ); 882 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION, 883 &l->ConstantAttenuation ); 884 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION, 885 &l->LinearAttenuation ); 886 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION, 887 &l->QuadraticAttenuation ); 888 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0; 889 } 890 891 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT, 892 ctx->Light.Model.Ambient ); 893 894 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx ); 895 896 for (i = 0 ; i < 6; i++) { 897 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL ); 898 } 899 900 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL ); 901 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density ); 902 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start ); 903 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End ); 904 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color ); 905 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL ); 906 907 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE; 908 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE; 909 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE; 910 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE; 911 912 rmesa->hw.eye.cmd[EYE_X] = 0; 913 rmesa->hw.eye.cmd[EYE_Y] = 0; 914 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE; 915 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE; 916 917 radeon_init_query_stateobj(&rmesa->radeon, R100_QUERYOBJ_CMDSIZE); 918 rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_CMD_0] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA, 0); 919 rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_DATA_0] = 0; 920 921 rmesa->radeon.hw.all_dirty = GL_TRUE; 922 923 rcommonInitCmdBuf(&rmesa->radeon); 924 } 925
