1 /** 2 * \file server/radeon_macros.h 3 * \brief Macros for Radeon MMIO operation. 4 * 5 * \authors Kevin E. Martin <martin (at) xfree86.org> 6 * \authors Rickard E. Faith <faith (at) valinux.com> 7 * \authors Alan Hourihane <alanh (at) fairlite.demon.co.uk> 8 */ 9 10 /* 11 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 12 * VA Linux Systems Inc., Fremont, California. 13 * 14 * All Rights Reserved. 15 * 16 * Permission is hereby granted, free of charge, to any person obtaining 17 * a copy of this software and associated documentation files (the 18 * "Software"), to deal in the Software without restriction, including 19 * without limitation on the rights to use, copy, modify, merge, 20 * publish, distribute, sublicense, and/or sell copies of the Software, 21 * and to permit persons to whom the Software is furnished to do so, 22 * subject to the following conditions: 23 * 24 * The above copyright notice and this permission notice (including the 25 * next paragraph) shall be included in all copies or substantial 26 * portions of the Software. 27 * 28 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 29 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 31 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 32 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 33 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 34 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 35 * DEALINGS IN THE SOFTWARE. 36 */ 37 38 39 #ifndef _RADEON_MACROS_H_ 40 #define _RADEON_MACROS_H_ 41 42 #include <mmio.h> 43 44 # define MMIO_IN8(base, offset) \ 45 *(volatile unsigned char *)(((unsigned char*)(base)) + (offset)) 46 # define MMIO_IN32(base, offset) \ 47 read_MMIO_LE32(base, offset) 48 # define MMIO_OUT8(base, offset, val) \ 49 *(volatile unsigned char *)(((unsigned char*)(base)) + (offset)) = (val) 50 # define MMIO_OUT32(base, offset, val) \ 51 *(volatile unsigned int *)(void *)(((unsigned char*)(base)) + (offset)) = CPU_TO_LE32(val) 52 53 54 /* Memory mapped register access macros */ 55 #define INREG8(addr) MMIO_IN8(RADEONMMIO, addr) 56 #define INREG(addr) MMIO_IN32(RADEONMMIO, addr) 57 #define OUTREG8(addr, val) MMIO_OUT8(RADEONMMIO, addr, val) 58 #define OUTREG(addr, val) MMIO_OUT32(RADEONMMIO, addr, val) 59 60 #define ADDRREG(addr) ((volatile GLuint *)(pointer)(RADEONMMIO + (addr))) 61 62 63 #define OUTREGP(addr, val, mask) \ 64 do { \ 65 GLuint tmp = INREG(addr); \ 66 tmp &= (mask); \ 67 tmp |= (val); \ 68 OUTREG(addr, tmp); \ 69 } while (0) 70 71 #define INPLL(dpy, addr) RADEONINPLL(dpy, addr) 72 73 #define OUTPLL(addr, val) \ 74 do { \ 75 OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | \ 76 RADEON_PLL_WR_EN)); \ 77 OUTREG(RADEON_CLOCK_CNTL_DATA, val); \ 78 } while (0) 79 80 #define OUTPLLP(dpy, addr, val, mask) \ 81 do { \ 82 GLuint tmp = INPLL(dpy, addr); \ 83 tmp &= (mask); \ 84 tmp |= (val); \ 85 OUTPLL(addr, tmp); \ 86 } while (0) 87 88 #define OUTPAL_START(idx) \ 89 do { \ 90 OUTREG8(RADEON_PALETTE_INDEX, (idx)); \ 91 } while (0) 92 93 #define OUTPAL_NEXT(r, g, b) \ 94 do { \ 95 OUTREG(RADEON_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b)); \ 96 } while (0) 97 98 #define OUTPAL_NEXT_CARD32(v) \ 99 do { \ 100 OUTREG(RADEON_PALETTE_DATA, (v & 0x00ffffff)); \ 101 } while (0) 102 103 #define OUTPAL(idx, r, g, b) \ 104 do { \ 105 OUTPAL_START((idx)); \ 106 OUTPAL_NEXT((r), (g), (b)); \ 107 } while (0) 108 109 #define INPAL_START(idx) \ 110 do { \ 111 OUTREG(RADEON_PALETTE_INDEX, (idx) << 16); \ 112 } while (0) 113 114 #define INPAL_NEXT() INREG(RADEON_PALETTE_DATA) 115 116 #define PAL_SELECT(idx) \ 117 do { \ 118 if (!idx) { \ 119 OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) & \ 120 (GLuint)~RADEON_DAC2_PALETTE_ACC_CTL); \ 121 } else { \ 122 OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) | \ 123 RADEON_DAC2_PALETTE_ACC_CTL); \ 124 } \ 125 } while (0) 126 127 128 #endif 129
