1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/block/fdc.h" 27 #include "hw/loader.h" 28 #include "hw/pci/pci.h" 29 #include "block/block.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/blockdev.h" 32 #include "audio/audio.h" 33 #include "net/net.h" 34 //#include "smbus.h" 35 #include "hw/boards.h" 36 #include "android/globals.h" 37 #include "monitor/monitor.h" 38 #include "hw/nvram/fw_cfg.h" 39 //#include "hpet_emul.h" 40 #include "sysemu/watchdog.h" 41 #include "hw/i386/smbios.h" 42 #include "ui/console.h" 43 44 #include "hw/android/goldfish/device.h" 45 #include "hw/android/goldfish/pipe.h" 46 47 char* audio_input_source = NULL; 48 /* output Bochs bios info messages */ 49 //#define DEBUG_BIOS 50 51 #define BIOS_FILENAME "bios.bin" 52 #define VGABIOS_FILENAME "vgabios.bin" 53 #define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin" 54 55 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) 56 57 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ 58 #define ACPI_DATA_SIZE 0x10000 59 #define BIOS_CFG_IOPORT 0x510 60 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 61 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 62 63 #define MAX_IDE_BUS 2 64 #ifndef CONFIG_ANDROID 65 static fdctrl_t *floppy_controller; 66 #endif 67 static RTCState *rtc_state; 68 static PITState *pit; 69 static IOAPICState *ioapic; 70 static PCIDevice *i440fx_state; 71 72 typedef struct rom_reset_data { 73 uint8_t *data; 74 hwaddr addr; 75 unsigned size; 76 } RomResetData; 77 78 static void option_rom_reset(void *_rrd) 79 { 80 RomResetData *rrd = _rrd; 81 82 cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size); 83 } 84 85 static void option_rom_setup_reset(hwaddr addr, unsigned size) 86 { 87 RomResetData *rrd = g_malloc(sizeof *rrd); 88 89 rrd->data = g_malloc(size); 90 cpu_physical_memory_read(addr, rrd->data, size); 91 rrd->addr = addr; 92 rrd->size = size; 93 qemu_register_reset(option_rom_reset, 0, rrd); 94 } 95 96 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) 97 { 98 } 99 100 /* MSDOS compatibility mode FPU exception support */ 101 static qemu_irq ferr_irq; 102 /* XXX: add IGNNE support */ 103 void cpu_set_ferr(CPUX86State *s) 104 { 105 qemu_irq_raise(ferr_irq); 106 } 107 108 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) 109 { 110 qemu_irq_lower(ferr_irq); 111 } 112 113 /* TSC handling */ 114 uint64_t cpu_get_tsc(CPUX86State *env) 115 { 116 return cpu_get_ticks(); 117 } 118 119 /* SMM support */ 120 void cpu_smm_update(CPUOldState *env) 121 { 122 if (i440fx_state && ENV_GET_CPU(env) == first_cpu) 123 i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1); 124 } 125 126 127 /* IRQ handling */ 128 int cpu_get_pic_interrupt(CPUOldState *env) 129 { 130 int intno; 131 132 intno = apic_get_interrupt(env); 133 if (intno >= 0) { 134 /* set irq request if a PIC irq is still pending */ 135 /* XXX: improve that */ 136 pic_update_irq(isa_pic); 137 return intno; 138 } 139 /* read the irq from the PIC */ 140 if (!apic_accept_pic_intr(env)) 141 return -1; 142 143 intno = pic_read_irq(isa_pic); 144 return intno; 145 } 146 147 static void pic_irq_request(void *opaque, int irq, int level) 148 { 149 CPUState *cpu = first_cpu; 150 CPUArchState *env = cpu->env_ptr; 151 152 if (env->apic_state) { 153 while (cpu) { 154 if (apic_accept_pic_intr(env)) 155 apic_deliver_pic_intr(env, level); 156 cpu = QTAILQ_NEXT(cpu, node); 157 env = cpu ? cpu->env_ptr : NULL; 158 } 159 } else { 160 if (level) 161 cpu_interrupt(cpu, CPU_INTERRUPT_HARD); 162 else 163 cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); 164 } 165 } 166 167 /* PC cmos mappings */ 168 169 #define REG_EQUIPMENT_BYTE 0x14 170 171 #ifndef CONFIG_ANDROID 172 static int cmos_get_fd_drive_type(int fd0) 173 { 174 int val; 175 176 switch (fd0) { 177 case 0: 178 /* 1.44 Mb 3"5 drive */ 179 val = 4; 180 break; 181 case 1: 182 /* 2.88 Mb 3"5 drive */ 183 val = 5; 184 break; 185 case 2: 186 /* 1.2 Mb 5"5 drive */ 187 val = 2; 188 break; 189 default: 190 val = 0; 191 break; 192 } 193 return val; 194 } 195 #endif 196 197 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd) 198 { 199 RTCState *s = rtc_state; 200 int cylinders, heads, sectors; 201 bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); 202 rtc_set_memory(s, type_ofs, 47); 203 rtc_set_memory(s, info_ofs, cylinders); 204 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 205 rtc_set_memory(s, info_ofs + 2, heads); 206 rtc_set_memory(s, info_ofs + 3, 0xff); 207 rtc_set_memory(s, info_ofs + 4, 0xff); 208 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 209 rtc_set_memory(s, info_ofs + 6, cylinders); 210 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 211 rtc_set_memory(s, info_ofs + 8, sectors); 212 } 213 214 /* convert boot_device letter to something recognizable by the bios */ 215 static int boot_device2nibble(char boot_device) 216 { 217 switch(boot_device) { 218 case 'a': 219 case 'b': 220 return 0x01; /* floppy boot */ 221 case 'c': 222 return 0x02; /* hard drive boot */ 223 case 'd': 224 return 0x03; /* CD-ROM boot */ 225 case 'n': 226 return 0x04; /* Network boot */ 227 } 228 return 0; 229 } 230 231 /* copy/pasted from cmos_init, should be made a general function 232 and used there as well */ 233 static int pc_boot_set(void *opaque, const char *boot_device) 234 { 235 Monitor *mon = cur_mon; 236 #define PC_MAX_BOOT_DEVICES 3 237 RTCState *s = (RTCState *)opaque; 238 int nbds, bds[3] = { 0, }; 239 int i; 240 241 nbds = strlen(boot_device); 242 if (nbds > PC_MAX_BOOT_DEVICES) { 243 monitor_printf(mon, "Too many boot devices for PC\n"); 244 return(1); 245 } 246 for (i = 0; i < nbds; i++) { 247 bds[i] = boot_device2nibble(boot_device[i]); 248 if (bds[i] == 0) { 249 monitor_printf(mon, "Invalid boot device for PC: '%c'\n", 250 boot_device[i]); 251 return(1); 252 } 253 } 254 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 255 rtc_set_memory(s, 0x38, (bds[2] << 4)); 256 return(0); 257 } 258 259 /* hd_table must contain 4 block drivers */ 260 static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 261 const char *boot_device, BlockDriverState **hd_table) 262 { 263 RTCState *s = rtc_state; 264 int nbds, bds[3] = { 0, }; 265 int val; 266 #ifndef CONFIG_ANDROID 267 int fd0, fd1, nb; 268 #endif 269 int i; 270 271 /* various important CMOS locations needed by PC/Bochs bios */ 272 273 /* memory size */ 274 val = 640; /* base memory in K */ 275 rtc_set_memory(s, 0x15, val); 276 rtc_set_memory(s, 0x16, val >> 8); 277 278 val = (ram_size / 1024) - 1024; 279 if (val > 65535) 280 val = 65535; 281 rtc_set_memory(s, 0x17, val); 282 rtc_set_memory(s, 0x18, val >> 8); 283 rtc_set_memory(s, 0x30, val); 284 rtc_set_memory(s, 0x31, val >> 8); 285 286 if (above_4g_mem_size) { 287 rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); 288 rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); 289 rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); 290 } 291 292 if (ram_size > (16 * 1024 * 1024)) 293 val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); 294 else 295 val = 0; 296 if (val > 65535) 297 val = 65535; 298 rtc_set_memory(s, 0x34, val); 299 rtc_set_memory(s, 0x35, val >> 8); 300 301 /* set the number of CPU */ 302 rtc_set_memory(s, 0x5f, smp_cpus - 1); 303 304 /* set boot devices, and disable floppy signature check if requested */ 305 #define PC_MAX_BOOT_DEVICES 3 306 nbds = strlen(boot_device); 307 if (nbds > PC_MAX_BOOT_DEVICES) { 308 fprintf(stderr, "Too many boot devices for PC\n"); 309 exit(1); 310 } 311 for (i = 0; i < nbds; i++) { 312 bds[i] = boot_device2nibble(boot_device[i]); 313 if (bds[i] == 0) { 314 fprintf(stderr, "Invalid boot device for PC: '%c'\n", 315 boot_device[i]); 316 exit(1); 317 } 318 } 319 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 320 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 321 322 /* floppy type */ 323 324 #ifndef CONFIG_ANDROID 325 fd0 = fdctrl_get_drive_type(floppy_controller, 0); 326 fd1 = fdctrl_get_drive_type(floppy_controller, 1); 327 328 val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1); 329 rtc_set_memory(s, 0x10, val); 330 331 val = 0; 332 nb = 0; 333 if (fd0 < 3) 334 nb++; 335 if (fd1 < 3) 336 nb++; 337 switch (nb) { 338 case 0: 339 break; 340 case 1: 341 val |= 0x01; /* 1 drive, ready for boot */ 342 break; 343 case 2: 344 val |= 0x41; /* 2 drives, ready for boot */ 345 break; 346 } 347 val |= 0x02; /* FPU is there */ 348 val |= 0x04; /* PS/2 mouse installed */ 349 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 350 #endif 351 352 /* hard drives */ 353 354 rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); 355 if (hd_table[0]) 356 cmos_init_hd(0x19, 0x1b, hd_table[0]); 357 if (hd_table[1]) 358 cmos_init_hd(0x1a, 0x24, hd_table[1]); 359 360 val = 0; 361 for (i = 0; i < 4; i++) { 362 if (hd_table[i]) { 363 int cylinders, heads, sectors, translation; 364 /* NOTE: bdrv_get_geometry_hint() returns the physical 365 geometry. It is always such that: 1 <= sects <= 63, 1 366 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 367 geometry can be different if a translation is done. */ 368 translation = bdrv_get_translation_hint(hd_table[i]); 369 if (translation == BIOS_ATA_TRANSLATION_AUTO) { 370 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, §ors); 371 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { 372 /* No translation. */ 373 translation = 0; 374 } else { 375 /* LBA translation. */ 376 translation = 1; 377 } 378 } else { 379 translation--; 380 } 381 val |= translation << (i * 2); 382 } 383 } 384 rtc_set_memory(s, 0x39, val); 385 } 386 387 void ioport_set_a20(int enable) 388 { 389 /* XXX: send to all CPUs ? */ 390 cpu_x86_set_a20(first_cpu->env_ptr, enable); 391 } 392 393 int ioport_get_a20(void) 394 { 395 CPUArchState *env = first_cpu->env_ptr; 396 return (env->a20_mask >> 20) & 1; 397 } 398 399 static void ioport92_write(void *opaque, uint32_t addr, uint32_t val) 400 { 401 ioport_set_a20((val >> 1) & 1); 402 /* XXX: bit 0 is fast reset */ 403 } 404 405 static uint32_t ioport92_read(void *opaque, uint32_t addr) 406 { 407 return ioport_get_a20() << 1; 408 } 409 410 /***********************************************************/ 411 /* Bochs BIOS debug ports */ 412 413 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) 414 { 415 static const char shutdown_str[8] = "Shutdown"; 416 static int shutdown_index = 0; 417 418 switch(addr) { 419 /* Bochs BIOS messages */ 420 case 0x400: 421 case 0x401: 422 fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val); 423 exit(1); 424 case 0x402: 425 case 0x403: 426 #ifdef DEBUG_BIOS 427 fprintf(stderr, "%c", val); 428 #endif 429 break; 430 case 0x8900: 431 /* same as Bochs power off */ 432 if (val == shutdown_str[shutdown_index]) { 433 shutdown_index++; 434 if (shutdown_index == 8) { 435 shutdown_index = 0; 436 qemu_system_shutdown_request(); 437 } 438 } else { 439 shutdown_index = 0; 440 } 441 break; 442 443 /* LGPL'ed VGA BIOS messages */ 444 case 0x501: 445 case 0x502: 446 fprintf(stderr, "VGA BIOS panic, line %d\n", val); 447 exit(1); 448 case 0x500: 449 case 0x503: 450 #ifdef DEBUG_BIOS 451 fprintf(stderr, "%c", val); 452 #endif 453 break; 454 } 455 } 456 457 extern uint64_t node_cpumask[MAX_NODES]; 458 459 static void bochs_bios_init(void) 460 { 461 void *fw_cfg; 462 uint8_t *smbios_table; 463 size_t smbios_len; 464 uint64_t *numa_fw_cfg; 465 int i, j; 466 467 register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); 468 register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); 469 register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); 470 register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); 471 register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); 472 473 register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); 474 register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); 475 register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); 476 register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); 477 478 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); 479 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 480 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 481 #ifndef CONFIG_ANDROID 482 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, 483 acpi_tables_len); 484 #endif 485 smbios_table = smbios_get_table(&smbios_len); 486 if (smbios_table) 487 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 488 smbios_table, smbios_len); 489 490 /* allocate memory for the NUMA channel: one (64bit) word for the number 491 * of nodes, one word for each VCPU->node and one word for each node to 492 * hold the amount of memory. 493 */ 494 numa_fw_cfg = g_malloc0((1 + smp_cpus + nb_numa_nodes) * 8); 495 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 496 for (i = 0; i < smp_cpus; i++) { 497 for (j = 0; j < nb_numa_nodes; j++) { 498 if (node_cpumask[j] & (1 << i)) { 499 numa_fw_cfg[i + 1] = cpu_to_le64(j); 500 break; 501 } 502 } 503 } 504 for (i = 0; i < nb_numa_nodes; i++) { 505 numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]); 506 } 507 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, 508 (1 + smp_cpus + nb_numa_nodes) * 8); 509 } 510 511 /* Generate an initial boot sector which sets state and jump to 512 a specified vector */ 513 static void generate_bootsect(hwaddr option_rom, 514 uint32_t gpr[8], uint16_t segs[6], uint16_t ip) 515 { 516 uint8_t rom[512], *p, *reloc; 517 uint8_t sum; 518 int i; 519 520 memset(rom, 0, sizeof(rom)); 521 522 p = rom; 523 /* Make sure we have an option rom signature */ 524 *p++ = 0x55; 525 *p++ = 0xaa; 526 527 /* ROM size in sectors*/ 528 *p++ = 1; 529 530 /* Hook int19 */ 531 532 *p++ = 0x50; /* push ax */ 533 *p++ = 0x1e; /* push ds */ 534 *p++ = 0x31; *p++ = 0xc0; /* xor ax, ax */ 535 *p++ = 0x8e; *p++ = 0xd8; /* mov ax, ds */ 536 537 *p++ = 0xc7; *p++ = 0x06; /* movvw _start,0x64 */ 538 *p++ = 0x64; *p++ = 0x00; 539 reloc = p; 540 *p++ = 0x00; *p++ = 0x00; 541 542 *p++ = 0x8c; *p++ = 0x0e; /* mov cs,0x66 */ 543 *p++ = 0x66; *p++ = 0x00; 544 545 *p++ = 0x1f; /* pop ds */ 546 *p++ = 0x58; /* pop ax */ 547 *p++ = 0xcb; /* lret */ 548 549 /* Actual code */ 550 *reloc = (p - rom); 551 552 *p++ = 0xfa; /* CLI */ 553 *p++ = 0xfc; /* CLD */ 554 555 for (i = 0; i < 6; i++) { 556 if (i == 1) /* Skip CS */ 557 continue; 558 559 *p++ = 0xb8; /* MOV AX,imm16 */ 560 *p++ = segs[i]; 561 *p++ = segs[i] >> 8; 562 *p++ = 0x8e; /* MOV <seg>,AX */ 563 *p++ = 0xc0 + (i << 3); 564 } 565 566 for (i = 0; i < 8; i++) { 567 *p++ = 0x66; /* 32-bit operand size */ 568 *p++ = 0xb8 + i; /* MOV <reg>,imm32 */ 569 *p++ = gpr[i]; 570 *p++ = gpr[i] >> 8; 571 *p++ = gpr[i] >> 16; 572 *p++ = gpr[i] >> 24; 573 } 574 575 *p++ = 0xea; /* JMP FAR */ 576 *p++ = ip; /* IP */ 577 *p++ = ip >> 8; 578 *p++ = segs[1]; /* CS */ 579 *p++ = segs[1] >> 8; 580 581 /* sign rom */ 582 sum = 0; 583 for (i = 0; i < (sizeof(rom) - 1); i++) 584 sum += rom[i]; 585 rom[sizeof(rom) - 1] = -sum; 586 587 cpu_physical_memory_write_rom(option_rom, rom, sizeof(rom)); 588 option_rom_setup_reset(option_rom, sizeof (rom)); 589 } 590 591 static long get_file_size(FILE *f) 592 { 593 long where, size; 594 595 /* XXX: on Unix systems, using fstat() probably makes more sense */ 596 597 where = ftell(f); 598 fseek(f, 0, SEEK_END); 599 size = ftell(f); 600 fseek(f, where, SEEK_SET); 601 602 return size; 603 } 604 605 static void load_linux(hwaddr option_rom, 606 const char *kernel_filename, 607 const char *initrd_filename, 608 const char *kernel_cmdline, 609 hwaddr max_ram_size) 610 { 611 uint16_t protocol; 612 uint32_t gpr[8]; 613 uint16_t seg[6]; 614 uint16_t real_seg; 615 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 616 uint32_t initrd_max; 617 uint8_t header[1024]; 618 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 619 FILE *f, *fi; 620 621 /* Align to 16 bytes as a paranoia measure */ 622 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 623 624 /* load the kernel header */ 625 f = fopen(kernel_filename, "rb"); 626 if (!f || !(kernel_size = get_file_size(f)) || 627 fread(header, 1, 1024, f) != 1024) { 628 fprintf(stderr, "qemu: could not load kernel '%s'\n", 629 kernel_filename); 630 exit(1); 631 } 632 633 /* kernel protocol version */ 634 #if 0 635 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 636 #endif 637 if (ldl_p(header+0x202) == 0x53726448) 638 protocol = lduw_p(header+0x206); 639 else 640 protocol = 0; 641 642 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 643 /* Low kernel */ 644 real_addr = 0x90000; 645 cmdline_addr = 0x9a000 - cmdline_size; 646 prot_addr = 0x10000; 647 } else if (protocol < 0x202) { 648 /* High but ancient kernel */ 649 real_addr = 0x90000; 650 cmdline_addr = 0x9a000 - cmdline_size; 651 prot_addr = 0x100000; 652 } else { 653 /* High and recent kernel */ 654 real_addr = 0x10000; 655 cmdline_addr = 0x20000; 656 prot_addr = 0x100000; 657 } 658 659 #if 0 660 fprintf(stderr, 661 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 662 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 663 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 664 real_addr, 665 cmdline_addr, 666 prot_addr); 667 #endif 668 669 /* highest address for loading the initrd */ 670 if (protocol >= 0x203) 671 initrd_max = ldl_p(header+0x22c); 672 else 673 initrd_max = 0x37ffffff; 674 675 if (initrd_max >= max_ram_size-ACPI_DATA_SIZE) 676 initrd_max = max_ram_size-ACPI_DATA_SIZE-1; 677 678 /* kernel command line */ 679 pstrcpy_targphys("cmdline", cmdline_addr, 4096, kernel_cmdline); 680 681 if (protocol >= 0x202) { 682 stl_p(header+0x228, cmdline_addr); 683 } else { 684 stw_p(header+0x20, 0xA33F); 685 stw_p(header+0x22, cmdline_addr-real_addr); 686 } 687 688 /* loader type */ 689 /* High nybble = B reserved for Qemu; low nybble is revision number. 690 If this code is substantially changed, you may want to consider 691 incrementing the revision. */ 692 if (protocol >= 0x200) 693 header[0x210] = 0xB0; 694 695 /* heap */ 696 if (protocol >= 0x201) { 697 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 698 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 699 } 700 701 /* load initrd */ 702 if (initrd_filename) { 703 if (protocol < 0x200) { 704 fprintf(stderr, "qemu: linux kernel too old to load a ram disk %s, %s, %s\n", 705 kernel_filename, initrd_filename, kernel_cmdline); 706 exit(1); 707 } 708 709 fi = fopen(initrd_filename, "rb"); 710 if (!fi) { 711 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 712 initrd_filename); 713 exit(1); 714 } 715 716 initrd_size = get_file_size(fi); 717 initrd_addr = (initrd_max-initrd_size) & ~4095; 718 719 if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) { 720 fprintf(stderr, "qemu: read error on initial ram disk '%s'\n", 721 initrd_filename); 722 exit(1); 723 } 724 fclose(fi); 725 726 stl_p(header+0x218, initrd_addr); 727 stl_p(header+0x21c, initrd_size); 728 } 729 730 /* store the finalized header and load the rest of the kernel */ 731 cpu_physical_memory_write(real_addr, header, 1024); 732 733 setup_size = header[0x1f1]; 734 if (setup_size == 0) 735 setup_size = 4; 736 737 setup_size = (setup_size+1)*512; 738 kernel_size -= setup_size; /* Size of protected-mode code */ 739 740 if (!fread_targphys_ok(real_addr+1024, setup_size-1024, f) || 741 !fread_targphys_ok(prot_addr, kernel_size, f)) { 742 fprintf(stderr, "qemu: read error on kernel '%s'\n", 743 kernel_filename); 744 exit(1); 745 } 746 fclose(f); 747 748 /* generate bootsector to set up the initial register state */ 749 real_seg = real_addr >> 4; 750 seg[0] = seg[2] = seg[3] = seg[4] = seg[5] = real_seg; 751 seg[1] = real_seg+0x20; /* CS */ 752 memset(gpr, 0, sizeof gpr); 753 gpr[4] = cmdline_addr-real_addr-16; /* SP (-16 is paranoia) */ 754 755 option_rom_setup_reset(real_addr, setup_size); 756 option_rom_setup_reset(prot_addr, kernel_size); 757 option_rom_setup_reset(cmdline_addr, cmdline_size); 758 if (initrd_filename) 759 option_rom_setup_reset(initrd_addr, initrd_size); 760 761 generate_bootsect(option_rom, gpr, seg, 0); 762 } 763 764 static void main_cpu_reset(void *opaque) 765 { 766 CPUOldState *env = opaque; 767 cpu_reset(ENV_GET_CPU(env)); 768 } 769 770 static const int ide_iobase[2] = { 0x1f0, 0x170 }; 771 static const int ide_iobase2[2] = { 0x3f6, 0x376 }; 772 static const int ide_irq[2] = { 14, 15 }; 773 774 #define NE2000_NB_MAX 6 775 776 static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; 777 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 778 779 /* static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; 780 static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; 781 782 static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; 783 static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; */ 784 785 #ifdef HAS_AUDIO 786 #ifndef CONFIG_ANDROID 787 static void audio_init (PCIBus *pci_bus, qemu_irq *pic) 788 { 789 struct soundhw *c; 790 791 for (c = soundhw; c->name; ++c) { 792 if (c->enabled) { 793 if (c->isa) { 794 c->init.init_isa(pic); 795 } else { 796 if (pci_bus) { 797 c->init.init_pci(pci_bus); 798 } 799 } 800 } 801 } 802 } 803 #endif 804 #endif 805 806 static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic) 807 { 808 static int nb_ne2k = 0; 809 810 if (nb_ne2k == NE2000_NB_MAX) 811 return; 812 isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd); 813 nb_ne2k++; 814 } 815 816 static int load_option_rom(const char *oprom, hwaddr start, 817 hwaddr end) 818 { 819 int size; 820 char *filename; 821 822 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, oprom); 823 if (filename) { 824 size = get_image_size(filename); 825 if (size > 0 && start + size > end) { 826 fprintf(stderr, "Not enough space to load option rom '%s'\n", 827 oprom); 828 exit(1); 829 } 830 size = load_image_targphys(filename, start, end - start); 831 g_free(filename); 832 } else { 833 size = -1; 834 } 835 if (size < 0) { 836 fprintf(stderr, "Could not load option rom '%s'\n", oprom); 837 exit(1); 838 } 839 /* Round up optiom rom size to the next 2k boundary */ 840 size = (size + 2047) & ~2047; 841 option_rom_setup_reset(start, size); 842 return size; 843 } 844 845 int cpu_is_bsp(CPUOldState *env) 846 { 847 return env->cpuid_apic_id == 0; 848 } 849 850 static struct goldfish_device event0_device = { 851 .name = "goldfish_events", 852 .id = 0, 853 .size = 0x1000, 854 /* FIXME: This is just a work around before we have a permanent fix on 855 * increasing number of IRQs available for x86 sysimages. IRQ3 is normally 856 * assigned to COM2/COM4, and we have our own custom IRQs for those. So, 857 * it's safe to reserve it for the events device. */ 858 .irq = 3, 859 .irq_count = 1 860 }; 861 862 static struct goldfish_device nand_device = { 863 .name = "goldfish_nand", 864 .id = 0, 865 .size = 0x1000 866 }; 867 868 /* PC hardware initialisation */ 869 static void pc_init1(ram_addr_t ram_size, 870 const char *boot_device, 871 const char *kernel_filename, const char *kernel_cmdline, 872 const char *initrd_filename, 873 int pci_enabled, const char *cpu_model) 874 { 875 char *filename; 876 int ret, linux_boot, i; 877 ram_addr_t ram_addr, bios_offset, option_rom_offset; 878 ram_addr_t below_4g_mem_size, above_4g_mem_size = 0; 879 int bios_size, isa_bios_size, oprom_area_size; 880 PCIBus *pci_bus; 881 int __attribute__((unused)) piix3_devfn = -1; 882 CPUOldState *env; 883 qemu_irq *cpu_irq; 884 qemu_irq *i8259; 885 #ifndef CONFIG_ANDROID 886 int index; 887 #endif 888 BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 889 #ifndef CONFIG_ANDROID 890 BlockDriverState *fd[MAX_FD]; 891 #endif 892 int using_vga = cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled; 893 894 if (ram_size >= 0xe0000000 ) { 895 above_4g_mem_size = ram_size - 0xe0000000; 896 below_4g_mem_size = 0xe0000000; 897 } else { 898 below_4g_mem_size = ram_size; 899 } 900 901 linux_boot = (kernel_filename != NULL); 902 903 /* init CPUs */ 904 if (cpu_model == NULL) { 905 #ifdef TARGET_X86_64 906 cpu_model = "qemu64"; 907 #else 908 cpu_model = "qemu32"; 909 #endif 910 } 911 912 for(i = 0; i < smp_cpus; i++) { 913 env = cpu_init(cpu_model); 914 if (!env) { 915 fprintf(stderr, "Unable to find x86 CPU definition\n"); 916 exit(1); 917 } 918 if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) { 919 env->cpuid_apic_id = ENV_GET_CPU(env)->cpu_index; 920 apic_init(env); 921 } 922 qemu_register_reset(main_cpu_reset, 0, env); 923 } 924 #ifndef CONFIG_ANDROID 925 vmport_init(); 926 927 /* allocate RAM */ 928 ram_addr = qemu_ram_alloc(NULL, "pc.ram", 929 below_4g_mem_size + above_4g_mem_size); 930 cpu_register_physical_memory(0, 0xa0000, ram_addr); 931 cpu_register_physical_memory(0x100000, 932 below_4g_mem_size - 0x100000, 933 ram_addr + 0x100000); 934 if (above_4g_mem_size > 0) { 935 cpu_register_physical_memory(0x100000000ULL, above_4g_mem_size, 936 ram_addr + below_4g_mem_size); 937 } 938 #else 939 /* 940 * Allocate a single contiguous RAM so that the goldfish 941 * framebuffer can work well especially when the frame buffer is 942 * large. 943 */ 944 ram_addr = qemu_ram_alloc(NULL, "pc.ram", below_4g_mem_size); 945 cpu_register_physical_memory(0, below_4g_mem_size, ram_addr); 946 #endif 947 948 /* above 4giga memory allocation */ 949 if (above_4g_mem_size > 0) { 950 #if TARGET_PHYS_ADDR_BITS == 32 951 hw_error("To much RAM for 32-bit physical address"); 952 #else 953 ram_addr = qemu_ram_alloc(above_4g_mem_size); 954 cpu_register_physical_memory(0x100000000ULL, 955 above_4g_mem_size, 956 ram_addr); 957 #endif 958 } 959 960 961 /* BIOS load */ 962 if (bios_name == NULL) 963 bios_name = BIOS_FILENAME; 964 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 965 if (filename) { 966 bios_size = get_image_size(filename); 967 } else { 968 bios_size = -1; 969 } 970 if (bios_size <= 0 || 971 (bios_size % 65536) != 0) { 972 goto bios_error; 973 } 974 bios_offset = qemu_ram_alloc(NULL, "bios.bin", bios_size); 975 ret = load_image(filename, qemu_get_ram_ptr(bios_offset)); 976 if (ret != bios_size) { 977 bios_error: 978 fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name); 979 exit(1); 980 } 981 if (filename) { 982 g_free(filename); 983 } 984 /* map the last 128KB of the BIOS in ISA space */ 985 isa_bios_size = bios_size; 986 if (isa_bios_size > (128 * 1024)) 987 isa_bios_size = 128 * 1024; 988 cpu_register_physical_memory(0x100000 - isa_bios_size, 989 isa_bios_size, 990 (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); 991 992 993 994 option_rom_offset = qemu_ram_alloc(NULL, "pc.rom", 0x20000); 995 oprom_area_size = 0; 996 cpu_register_physical_memory(0xc0000, 0x20000, option_rom_offset); 997 998 if (using_vga) { 999 const char *vgabios_filename; 1000 /* VGA BIOS load */ 1001 if (cirrus_vga_enabled) { 1002 vgabios_filename = VGABIOS_CIRRUS_FILENAME; 1003 } else { 1004 vgabios_filename = VGABIOS_FILENAME; 1005 } 1006 oprom_area_size = load_option_rom(vgabios_filename, 0xc0000, 0xe0000); 1007 } 1008 /* Although video roms can grow larger than 0x8000, the area between 1009 * 0xc0000 - 0xc8000 is reserved for them. It means we won't be looking 1010 * for any other kind of option rom inside this area */ 1011 if (oprom_area_size < 0x8000) 1012 oprom_area_size = 0x8000; 1013 1014 if (linux_boot) { 1015 load_linux(0xc0000 + oprom_area_size, 1016 kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); 1017 oprom_area_size += 2048; 1018 } 1019 1020 for (i = 0; i < nb_option_roms; i++) { 1021 oprom_area_size += load_option_rom(option_rom[i], 1022 0xc0000 + oprom_area_size, 0xe0000); 1023 } 1024 1025 /* map all the bios at the top of memory */ 1026 cpu_register_physical_memory((uint32_t)(-bios_size), 1027 bios_size, bios_offset | IO_MEM_ROM); 1028 1029 bochs_bios_init(); 1030 1031 cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1); 1032 i8259 = i8259_init(cpu_irq[0]); 1033 ferr_irq = i8259[GFD_ERR_IRQ]; 1034 1035 #define IRQ_PDEV_BUS 4 1036 goldfish_device_init(i8259, 0xff010000, 0x7f0000, 5, 5); 1037 goldfish_device_bus_init(0xff001000, IRQ_PDEV_BUS); 1038 1039 goldfish_battery_init(android_hw->hw_battery); 1040 1041 #ifdef CONFIG_NAND 1042 goldfish_add_device_no_io(&nand_device); 1043 nand_dev_init(nand_device.base); 1044 #endif 1045 bool newDeviceNaming = 1046 (androidHwConfig_getKernelDeviceNaming(android_hw) >= 1); 1047 pipe_dev_init(newDeviceNaming); 1048 1049 { 1050 DriveInfo* info = drive_get( IF_IDE, 0, 0 ); 1051 if (info != NULL) { 1052 goldfish_mmc_init(0xff005000, 0, info->bdrv); 1053 } 1054 } 1055 1056 if (pci_enabled) { 1057 pci_bus = i440fx_init(&i440fx_state, i8259); 1058 piix3_devfn = piix3_init(pci_bus, -1); 1059 } else { 1060 pci_bus = NULL; 1061 } 1062 1063 /* init basic PC hardware */ 1064 register_ioport_write(0x80, 1, 1, ioport80_write, NULL); 1065 1066 register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); 1067 1068 #ifndef CONFIG_ANDROID 1069 if (cirrus_vga_enabled) { 1070 if (pci_enabled) { 1071 pci_cirrus_vga_init(pci_bus); 1072 } else { 1073 isa_cirrus_vga_init(); 1074 } 1075 } else if (vmsvga_enabled) { 1076 if (pci_enabled) 1077 pci_vmsvga_init(pci_bus); 1078 else 1079 fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__); 1080 } else if (std_vga_enabled) { 1081 if (pci_enabled) { 1082 pci_vga_init(pci_bus, 0, 0); 1083 } else { 1084 isa_vga_init(); 1085 } 1086 } 1087 #endif 1088 1089 rtc_state = rtc_init(0x70, i8259[8], 2000); 1090 1091 qemu_register_boot_set(pc_boot_set, rtc_state); 1092 1093 register_ioport_read(0x92, 1, 1, ioport92_read, NULL); 1094 register_ioport_write(0x92, 1, 1, ioport92_write, NULL); 1095 1096 if (pci_enabled) { 1097 ioapic = ioapic_init(); 1098 } 1099 pit = pit_init(0x40, i8259[0]); 1100 1101 #ifndef CONFIG_ANDROID 1102 pcspk_init(pit); 1103 1104 if (!no_hpet) { 1105 hpet_init(i8259); 1106 } 1107 #endif 1108 1109 if (pci_enabled) { 1110 pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic); 1111 } 1112 1113 goldfish_tty_add(serial_hds[0], 0, 0, 0); 1114 /* FIXME: This is just a work around before we have a permanent fix on 1115 * increasing number of IRQs available for x86 sysimages. In order to free up 1116 * some IRQs for a better use, we limit number of TTY devices by 2. Normally 1117 * we don't need more than that, so always having 4 of them would waste two 1118 * precious IRQs. */ 1119 #if 0 1120 for(i = 1; i < MAX_SERIAL_PORTS; i++) { 1121 #else 1122 for(i = 1; i < 2; i++) { 1123 #endif 1124 if(serial_hds[i]) { 1125 goldfish_tty_add(serial_hds[i], i, 0, 0); 1126 } 1127 } 1128 1129 #ifndef CONFIG_ANDROID 1130 for(i = 0; i < MAX_SERIAL_PORTS; i++) { 1131 if (serial_hds[i]) { 1132 serial_init(serial_io[i], i8259[serial_irq[i]], 115200, 1133 serial_hds[i]); 1134 } 1135 } 1136 1137 for(i = 0; i < MAX_PARALLEL_PORTS; i++) { 1138 if (parallel_hds[i]) { 1139 parallel_init(parallel_io[i], i8259[parallel_irq[i]], 1140 parallel_hds[i]); 1141 } 1142 } 1143 #endif 1144 1145 watchdog_pc_init(pci_bus); 1146 1147 for(i = 0; i < nb_nics; i++) { 1148 NICInfo *nd = &nd_table[i]; 1149 1150 if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) 1151 pc_init_ne2k_isa(nd, i8259); 1152 else 1153 pci_nic_init(pci_bus, nd, -1, "ne2k_pci"); 1154 } 1155 1156 #ifdef CONFIG_ANDROID 1157 for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) 1158 hd[i] = NULL; 1159 #else 1160 qemu_system_hot_add_init(); 1161 1162 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { 1163 fprintf(stderr, "qemu: too many IDE bus\n"); 1164 exit(1); 1165 } 1166 1167 for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { 1168 index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); 1169 if (index != -1) 1170 hd[i] = drives_table[index].bdrv; 1171 else 1172 hd[i] = NULL; 1173 } 1174 1175 if (pci_enabled) { 1176 pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259); 1177 } else { 1178 for(i = 0; i < MAX_IDE_BUS; i++) { 1179 isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], 1180 hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]); 1181 } 1182 } 1183 #endif 1184 1185 i8042_init(i8259[GFD_KBD_IRQ], i8259[GFD_MOUSE_IRQ], 0x60); 1186 DMA_init(0); 1187 1188 goldfish_fb_init(0); 1189 1190 goldfish_add_device_no_io(&event0_device); 1191 events_dev_init(event0_device.base, i8259[event0_device.irq]); 1192 1193 #ifdef HAS_AUDIO 1194 #ifndef CONFIG_ANDROID 1195 audio_init(pci_enabled ? pci_bus : NULL, i8259); 1196 #else 1197 goldfish_audio_init(0xff004000, 0, audio_input_source); 1198 #endif 1199 #endif 1200 1201 #ifndef CONFIG_ANDROID 1202 for(i = 0; i < MAX_FD; i++) { 1203 index = drive_get_index(IF_FLOPPY, 0, i); 1204 if (index != -1) 1205 fd[i] = drives_table[index].bdrv; 1206 else 1207 fd[i] = NULL; 1208 } 1209 1210 floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd); 1211 #endif 1212 1213 cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd); 1214 1215 #ifndef CONFIG_ANDROID 1216 if (pci_enabled && usb_enabled) { 1217 usb_uhci_piix3_init(pci_bus, piix3_devfn + 2); 1218 } 1219 1220 if (pci_enabled && acpi_enabled) { 1221 uint8_t *eeprom_buf = g_malloc0(8 * 256); /* XXX: make this persistent */ 1222 i2c_bus *smbus; 1223 1224 /* TODO: Populate SPD eeprom data. */ 1225 smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]); 1226 for (i = 0; i < 8; i++) { 1227 DeviceState *eeprom; 1228 eeprom = qdev_create((BusState *)smbus, "smbus-eeprom"); 1229 qdev_set_prop_int(eeprom, "address", 0x50 + i); 1230 qdev_set_prop_ptr(eeprom, "data", eeprom_buf + (i * 256)); 1231 qdev_init(eeprom); 1232 } 1233 } 1234 #endif 1235 1236 if (i440fx_state) { 1237 i440fx_init_memory_mappings(i440fx_state); 1238 } 1239 1240 if (pci_enabled) { 1241 int max_bus; 1242 int bus; 1243 1244 max_bus = drive_get_max_bus(IF_SCSI); 1245 for (bus = 0; bus <= max_bus; bus++) { 1246 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1247 } 1248 } 1249 #ifndef CONFIG_ANDROID 1250 /* Add virtio block devices */ 1251 if (pci_enabled) { 1252 int index; 1253 int unit_id = 0; 1254 1255 while ((index = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) { 1256 pci_create_simple(pci_bus, -1, "virtio-blk-pci"); 1257 unit_id++; 1258 } 1259 } 1260 1261 /* Add virtio balloon device */ 1262 if (pci_enabled && !no_virtio_balloon) { 1263 pci_create_simple(pci_bus, -1, "virtio-balloon-pci"); 1264 } 1265 1266 /* Add virtio console devices */ 1267 if (pci_enabled) { 1268 for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) { 1269 if (virtcon_hds[i]) { 1270 pci_create_simple(pci_bus, -1, "virtio-console-pci"); 1271 } 1272 } 1273 } 1274 #endif 1275 } 1276 1277 static void pc_init_pci(ram_addr_t ram_size, 1278 const char *boot_device, 1279 const char *kernel_filename, 1280 const char *kernel_cmdline, 1281 const char *initrd_filename, 1282 const char *cpu_model) 1283 { 1284 pc_init1(ram_size, boot_device, 1285 kernel_filename, kernel_cmdline, 1286 initrd_filename, 1, cpu_model); 1287 } 1288 1289 static void pc_init_isa(ram_addr_t ram_size, 1290 const char *boot_device, 1291 const char *kernel_filename, 1292 const char *kernel_cmdline, 1293 const char *initrd_filename, 1294 const char *cpu_model) 1295 { 1296 pc_init1(ram_size, boot_device, 1297 kernel_filename, kernel_cmdline, 1298 initrd_filename, 0, cpu_model); 1299 } 1300 1301 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) 1302 BIOS will read it and start S3 resume at POST Entry */ 1303 void cmos_set_s3_resume(void) 1304 { 1305 if (rtc_state) 1306 rtc_set_memory(rtc_state, 0xF, 0xFE); 1307 } 1308 1309 static QEMUMachine pc_machine = { 1310 .name = "pc", 1311 .desc = "Standard PC", 1312 .init = pc_init_pci, 1313 .max_cpus = 255, 1314 .is_default = 1, 1315 }; 1316 1317 static QEMUMachine isapc_machine = { 1318 .name = "isapc", 1319 .desc = "ISA-only PC", 1320 .init = pc_init_isa, 1321 .max_cpus = 1, 1322 }; 1323 1324 static void pc_machine_init(void) 1325 { 1326 qemu_register_machine(&pc_machine); 1327 qemu_register_machine(&isapc_machine); 1328 } 1329 1330 machine_init(pc_machine_init); 1331
