1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _LINUX_DSSCOMP_H 20 #define _LINUX_DSSCOMP_H 21 enum omap_plane { 22 OMAP_DSS_GFX = 0, 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 OMAP_DSS_VIDEO1 = 1, 25 OMAP_DSS_VIDEO2 = 2, 26 OMAP_DSS_VIDEO3 = 3, 27 OMAP_DSS_WB = 4, 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 }; 30 enum omap_channel { 31 OMAP_DSS_CHANNEL_LCD = 0, 32 OMAP_DSS_CHANNEL_DIGIT = 1, 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 OMAP_DSS_CHANNEL_LCD2 = 2, 35 }; 36 enum omap_color_mode { 37 OMAP_DSS_COLOR_CLUT1 = 1 << 0, 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 OMAP_DSS_COLOR_CLUT2 = 1 << 1, 40 OMAP_DSS_COLOR_CLUT4 = 1 << 2, 41 OMAP_DSS_COLOR_CLUT8 = 1 << 3, 42 OMAP_DSS_COLOR_RGB12U = 1 << 4, 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 OMAP_DSS_COLOR_ARGB16 = 1 << 5, 45 OMAP_DSS_COLOR_RGB16 = 1 << 6, 46 OMAP_DSS_COLOR_RGB24U = 1 << 7, 47 OMAP_DSS_COLOR_RGB24P = 1 << 8, 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 OMAP_DSS_COLOR_YUV2 = 1 << 9, 50 OMAP_DSS_COLOR_UYVY = 1 << 10, 51 OMAP_DSS_COLOR_ARGB32 = 1 << 11, 52 OMAP_DSS_COLOR_RGBA32 = 1 << 12, 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 OMAP_DSS_COLOR_RGBX24 = 1 << 13, 55 OMAP_DSS_COLOR_RGBX32 = 1 << 13, 56 OMAP_DSS_COLOR_NV12 = 1 << 14, 57 OMAP_DSS_COLOR_RGBA16 = 1 << 15, 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 OMAP_DSS_COLOR_RGBX12 = 1 << 16, 60 OMAP_DSS_COLOR_RGBX16 = 1 << 16, 61 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, 62 OMAP_DSS_COLOR_XRGB15 = 1 << 18, 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, 65 }; 66 enum omap_writeback_source { 67 OMAP_WB_LCD1 = 0, 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 OMAP_WB_TV = 1, 70 OMAP_WB_LCD2 = 2, 71 OMAP_WB_GFX = 3, 72 OMAP_WB_VID1 = 4, 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 OMAP_WB_VID2 = 5, 75 OMAP_WB_VID3 = 6 76 }; 77 enum omap_writeback_mode { 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 OMAP_WB_CAPTURE_MODE = 0x0, 80 OMAP_WB_MEM2MEM_MODE = 0x1, 81 }; 82 enum omap_dss_trans_key_type { 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 OMAP_DSS_COLOR_KEY_GFX_DST = 0, 85 OMAP_DSS_COLOR_KEY_VID_SRC = 1, 86 }; 87 enum omap_dss_display_state { 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 OMAP_DSS_DISPLAY_DISABLED = 0, 90 OMAP_DSS_DISPLAY_ACTIVE, 91 OMAP_DSS_DISPLAY_SUSPENDED, 92 OMAP_DSS_DISPLAY_TRANSITION, 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 }; 95 struct omap_video_timings { 96 __u16 x_res; 97 __u16 y_res; 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 __u32 pixel_clock; 100 __u16 hsw; 101 __u16 hfp; 102 __u16 hbp; 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 __u16 vsw; 105 __u16 vfp; 106 __u16 vbp; 107 }; 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 struct omap_dss_cconv_coefs { 110 __s16 ry, rcr, rcb; 111 __s16 gy, gcr, gcb; 112 __s16 by, bcr, bcb; 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 __u16 full_range; 115 } __attribute__ ((aligned(4))); 116 struct omap_dss_cpr_coefs { 117 __s16 rr, rg, rb; 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 __s16 gr, gg, gb; 120 __s16 br, bg, bb; 121 }; 122 struct dsscomp_videomode { 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 const char *name; 125 __u32 refresh; 126 __u32 xres; 127 __u32 yres; 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 __u32 pixclock; 130 __u32 left_margin; 131 __u32 right_margin; 132 __u32 upper_margin; 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 __u32 lower_margin; 135 __u32 hsync_len; 136 __u32 vsync_len; 137 __u32 sync; 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 __u32 vmode; 140 __u32 flag; 141 }; 142 enum s3d_disp_type { 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 S3D_DISP_NONE = 0, 145 S3D_DISP_FRAME_SEQ, 146 S3D_DISP_ROW_IL, 147 S3D_DISP_COL_IL, 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 S3D_DISP_PIX_IL, 150 S3D_DISP_CHECKB, 151 S3D_DISP_OVERUNDER, 152 S3D_DISP_SIDEBYSIDE, 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 }; 155 enum s3d_disp_sub_sampling { 156 S3D_DISP_SUB_SAMPLE_NONE = 0, 157 S3D_DISP_SUB_SAMPLE_V, 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 S3D_DISP_SUB_SAMPLE_H, 160 }; 161 enum s3d_disp_order { 162 S3D_DISP_ORDER_L = 0, 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 S3D_DISP_ORDER_R = 1, 165 }; 166 enum s3d_disp_view { 167 S3D_DISP_VIEW_L = 0, 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 S3D_DISP_VIEW_R, 170 }; 171 struct s3d_disp_info { 172 enum s3d_disp_type type; 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 enum s3d_disp_sub_sampling sub_samp; 175 enum s3d_disp_order order; 176 unsigned int gap; 177 }; 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 enum omap_dss_ilace_mode { 180 OMAP_DSS_ILACE = (1 << 0), 181 OMAP_DSS_ILACE_SEQ = (1 << 1), 182 OMAP_DSS_ILACE_SWAP = (1 << 2), 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 OMAP_DSS_ILACE_NONE = 0, 185 OMAP_DSS_ILACE_IL_TB = OMAP_DSS_ILACE, 186 OMAP_DSS_ILACE_IL_BT = OMAP_DSS_ILACE | OMAP_DSS_ILACE_SWAP, 187 OMAP_DSS_ILACE_SEQ_TB = OMAP_DSS_ILACE_IL_TB | OMAP_DSS_ILACE_SEQ, 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 OMAP_DSS_ILACE_SEQ_BT = OMAP_DSS_ILACE_IL_BT | OMAP_DSS_ILACE_SEQ, 190 }; 191 struct dss2_vc1_range_map_info { 192 __u8 enable; 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 __u8 range_y; 195 __u8 range_uv; 196 } __attribute__ ((aligned(4))); 197 struct dss2_rect_t { 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 __s32 x; 200 __s32 y; 201 __u32 w; 202 __u32 h; 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 } __attribute__ ((aligned(4))); 205 struct dss2_decim { 206 __u8 min_x; 207 __u8 max_x; 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 __u8 min_y; 210 __u8 max_y; 211 } __attribute__ ((aligned(4))); 212 struct dss2_ovl_cfg { 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 __u16 width; 215 __u16 height; 216 __u32 stride; 217 enum omap_color_mode color_mode; 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 __u8 pre_mult_alpha; 220 __u8 global_alpha; 221 __u8 rotation; 222 __u8 mirror; 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 enum omap_dss_ilace_mode ilace; 225 struct dss2_rect_t win; 226 struct dss2_rect_t crop; 227 struct dss2_decim decim; 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 struct omap_dss_cconv_coefs cconv; 230 struct dss2_vc1_range_map_info vc1; 231 __u8 wb_source; 232 enum omap_writeback_mode wb_mode; 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 __u8 ix; 235 __u8 zorder; 236 __u8 enabled; 237 __u8 zonly; 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 __u8 mgr_ix; 240 } __attribute__ ((aligned(4))); 241 enum omapdss_buffer_type { 242 OMAP_DSS_BUFTYPE_SDMA, 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 OMAP_DSS_BUFTYPE_TILER_8BIT, 245 OMAP_DSS_BUFTYPE_TILER_16BIT, 246 OMAP_DSS_BUFTYPE_TILER_32BIT, 247 OMAP_DSS_BUFTYPE_TILER_PAGE, 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 }; 250 enum omapdss_buffer_addressing_type { 251 OMAP_DSS_BUFADDR_DIRECT, 252 OMAP_DSS_BUFADDR_BYTYPE, 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 OMAP_DSS_BUFADDR_ION, 255 OMAP_DSS_BUFADDR_GRALLOC, 256 OMAP_DSS_BUFADDR_OVL_IX, 257 OMAP_DSS_BUFADDR_LAYER_IX, 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 OMAP_DSS_BUFADDR_FB, 260 }; 261 struct dss2_ovl_info { 262 struct dss2_ovl_cfg cfg; 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 enum omapdss_buffer_addressing_type addressing; 265 union { 266 struct { 267 void *address; 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 void *uv_address; 270 }; 271 struct { 272 enum omapdss_buffer_type ba_type; 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 enum omapdss_buffer_type uv_type; 275 }; 276 struct { 277 __u32 ba; 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 __u32 uv; 280 }; 281 }; 282 }; 283 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 struct dss2_mgr_info { 285 __u32 ix; 286 __u32 default_color; 287 enum omap_dss_trans_key_type trans_key_type; 288 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 __u32 trans_key; 290 struct omap_dss_cpr_coefs cpr_coefs; 291 __u8 trans_enabled; 292 __u8 interlaced; 293 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 __u8 alpha_blending; 295 __u8 cpr_enabled; 296 __u8 swap_rb; 297 } __attribute__ ((aligned(4))); 298 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 enum dsscomp_setup_mode { 300 DSSCOMP_SETUP_MODE_APPLY = (1 << 0), 301 DSSCOMP_SETUP_MODE_DISPLAY = (1 << 1), 302 DSSCOMP_SETUP_MODE_CAPTURE = (1 << 2), 303 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 DSSCOMP_SETUP_APPLY = DSSCOMP_SETUP_MODE_APPLY, 305 DSSCOMP_SETUP_DISPLAY = 306 DSSCOMP_SETUP_MODE_APPLY | DSSCOMP_SETUP_MODE_DISPLAY, 307 DSSCOMP_SETUP_CAPTURE = 308 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309 DSSCOMP_SETUP_MODE_APPLY | DSSCOMP_SETUP_MODE_CAPTURE, 310 DSSCOMP_SETUP_DISPLAY_CAPTURE = 311 DSSCOMP_SETUP_DISPLAY | DSSCOMP_SETUP_CAPTURE, 312 }; 313 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 struct dsscomp_setup_mgr_data { 315 __u32 sync_id; 316 struct dss2_rect_t win; 317 enum dsscomp_setup_mode mode; 318 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 __u16 num_ovls; 320 __u16 get_sync_obj; 321 struct dss2_mgr_info mgr; 322 struct dss2_ovl_info ovls[0]; 323 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 }; 325 struct dsscomp_check_ovl_data { 326 enum dsscomp_setup_mode mode; 327 struct dss2_mgr_info mgr; 328 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 struct dss2_ovl_info ovl; 330 }; 331 struct dsscomp_setup_dispc_data { 332 __u32 sync_id; 333 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 enum dsscomp_setup_mode mode; 335 __u16 num_ovls; 336 __u16 num_mgrs; 337 __u16 get_sync_obj; 338 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 struct dss2_mgr_info mgrs[3]; 340 struct dss2_ovl_info ovls[5]; 341 }; 342 struct dsscomp_wb_copy_data { 343 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 struct dss2_ovl_info ovl, wb; 345 }; 346 struct dsscomp_display_info { 347 __u32 ix; 348 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 __u32 overlays_available; 350 __u32 overlays_owned; 351 enum omap_channel channel; 352 enum omap_dss_display_state state; 353 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354 __u8 enabled; 355 struct omap_video_timings timings; 356 struct s3d_disp_info s3d_info; 357 struct dss2_mgr_info mgr; 358 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359 __u16 width_in_mm; 360 __u16 height_in_mm; 361 __u32 modedb_len; 362 struct dsscomp_videomode modedb[]; 363 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 }; 365 struct dsscomp_setup_display_data { 366 __u32 ix; 367 struct dsscomp_videomode mode; 368 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 }; 370 enum dsscomp_wait_phase { 371 DSSCOMP_WAIT_PROGRAMMED = 1, 372 DSSCOMP_WAIT_DISPLAYED, 373 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 DSSCOMP_WAIT_RELEASED, 375 }; 376 struct dsscomp_wait_data { 377 __u32 timeout_us; 378 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 enum dsscomp_wait_phase phase; 380 }; 381 enum dsscomp_fbmem_type { 382 DSSCOMP_FBMEM_TILER2D = 0, 383 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 DSSCOMP_FBMEM_VRAM = 1, 385 }; 386 struct dsscomp_platform_info { 387 __u8 max_xdecim_2d; 388 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 __u8 max_ydecim_2d; 390 __u8 max_xdecim_1d; 391 __u8 max_ydecim_1d; 392 __u32 fclk; 393 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 __u8 min_width; 395 __u16 max_width; 396 __u16 max_height; 397 __u8 max_downscale; 398 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399 __u16 integer_scale_ratio_limit; 400 __u32 tiler1d_slot_size; 401 enum dsscomp_fbmem_type fbmem_type; 402 }; 403 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 #define DSSCIOC_SETUP_MGR _IOW('O', 128, struct dsscomp_setup_mgr_data) 405 #define DSSCIOC_CHECK_OVL _IOWR('O', 129, struct dsscomp_check_ovl_data) 406 #define DSSCIOC_WB_COPY _IOW('O', 130, struct dsscomp_wb_copy_data) 407 #define DSSCIOC_QUERY_DISPLAY _IOWR('O', 131, struct dsscomp_display_info) 408 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409 #define DSSCIOC_WAIT _IOW('O', 132, struct dsscomp_wait_data) 410 #define DSSCIOC_SETUP_DISPC _IOW('O', 133, struct dsscomp_setup_dispc_data) 411 #define DSSCIOC_SETUP_DISPLAY _IOW('O', 134, struct dsscomp_setup_display_data) 412 #define DSSCIOC_QUERY_PLATFORM _IOR('O', 135, struct dsscomp_platform_info) 413 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414 #endif 415
