1 #ifndef _ASM_X86_MCE_H 2 #define _ASM_X86_MCE_H 3 4 #include <linux/types.h> 5 #include <asm/ioctls.h> 6 7 /* 8 * Machine Check support for x86 9 */ 10 11 #define MCG_BANKCNT_MASK 0xff /* Number of Banks */ 12 #define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */ 13 #define MCG_EXT_P (1ULL<<9) /* Extended registers available */ 14 #define MCG_CMCI_P (1ULL<<10) /* CMCI supported */ 15 #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */ 16 #define MCG_EXT_CNT_SHIFT 16 17 #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT) 18 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 19 20 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 21 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 22 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 23 24 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 25 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 26 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 27 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 28 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 29 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 30 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 31 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 32 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 33 34 /* MISC register defines */ 35 #define MCM_ADDR_SEGOFF 0 /* segment offset */ 36 #define MCM_ADDR_LINEAR 1 /* linear address */ 37 #define MCM_ADDR_PHYS 2 /* physical address */ 38 #define MCM_ADDR_MEM 3 /* memory address */ 39 #define MCM_ADDR_GENERIC 7 /* generic */ 40 41 #define MCJ_CTX_MASK 3 42 #define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK) 43 #define MCJ_CTX_RANDOM 0 /* inject context: random */ 44 #define MCJ_CTX_PROCESS 1 /* inject context: process */ 45 #define MCJ_CTX_IRQ 2 /* inject context: IRQ */ 46 #define MCJ_NMI_BROADCAST 4 /* do NMI broadcasting */ 47 #define MCJ_EXCEPTION 8 /* raise as exception */ 48 49 /* Fields are zero when not available */ 50 struct mce { 51 __u64 status; 52 __u64 misc; 53 __u64 addr; 54 __u64 mcgstatus; 55 __u64 ip; 56 __u64 tsc; /* cpu time stamp counter */ 57 __u64 time; /* wall time_t when error was detected */ 58 __u8 cpuvendor; /* cpu vendor as encoded in system.h */ 59 __u8 inject_flags; /* software inject flags */ 60 __u16 pad; 61 __u32 cpuid; /* CPUID 1 EAX */ 62 __u8 cs; /* code segment */ 63 __u8 bank; /* machine check bank */ 64 __u8 cpu; /* cpu number; obsolete; use extcpu now */ 65 __u8 finished; /* entry is valid */ 66 __u32 extcpu; /* linux cpu number that detected the error */ 67 __u32 socketid; /* CPU socket ID */ 68 __u32 apicid; /* CPU initial apic ID */ 69 __u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */ 70 __u64 aux0; /* model specific */ 71 __u64 aux1; /* model specific */ 72 }; 73 74 /* 75 * This structure contains all data related to the MCE log. Also 76 * carries a signature to make it easier to find from external 77 * debugging tools. Each entry is only valid when its finished flag 78 * is set. 79 */ 80 81 #define MCE_LOG_LEN 32 82 83 struct mce_log { 84 char signature[12]; /* "MACHINECHECK" */ 85 unsigned len; /* = MCE_LOG_LEN */ 86 unsigned next; 87 unsigned flags; 88 unsigned recordlen; /* length of struct mce */ 89 struct mce entry[MCE_LOG_LEN]; 90 }; 91 92 #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */ 93 94 #define MCE_LOG_SIGNATURE "MACHINECHECK" 95 96 #define MCE_GET_RECORD_LEN _IOR('M', 1, int) 97 #define MCE_GET_LOG_LEN _IOR('M', 2, int) 98 #define MCE_GETCLEAR_FLAGS _IOR('M', 3, int) 99 100 /* Software defined banks */ 101 #define MCE_EXTENDED_BANK 128 102 #define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0 103 104 #define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */ 105 #define K8_MCE_THRESHOLD_BANK_0 (MCE_THRESHOLD_BASE + 0 * 9) 106 #define K8_MCE_THRESHOLD_BANK_1 (MCE_THRESHOLD_BASE + 1 * 9) 107 #define K8_MCE_THRESHOLD_BANK_2 (MCE_THRESHOLD_BASE + 2 * 9) 108 #define K8_MCE_THRESHOLD_BANK_3 (MCE_THRESHOLD_BASE + 3 * 9) 109 #define K8_MCE_THRESHOLD_BANK_4 (MCE_THRESHOLD_BASE + 4 * 9) 110 #define K8_MCE_THRESHOLD_BANK_5 (MCE_THRESHOLD_BASE + 5 * 9) 111 #define K8_MCE_THRESHOLD_DRAM_ECC (MCE_THRESHOLD_BANK_4 + 0) 112 113 #endif /* _ASM_X86_MCE_H */ 114
