1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _ASM_IRQ_GT641XX_H 20 #define _ASM_IRQ_GT641XX_H 21 #ifndef GT641XX_IRQ_BASE 22 #define GT641XX_IRQ_BASE 8 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #endif 25 #define GT641XX_MEMORY_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 1) 26 #define GT641XX_DMA_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 2) 27 #define GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 3) 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #define GT641XX_DMA0_IRQ (GT641XX_IRQ_BASE + 4) 30 #define GT641XX_DMA1_IRQ (GT641XX_IRQ_BASE + 5) 31 #define GT641XX_DMA2_IRQ (GT641XX_IRQ_BASE + 6) 32 #define GT641XX_DMA3_IRQ (GT641XX_IRQ_BASE + 7) 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define GT641XX_TIMER0_IRQ (GT641XX_IRQ_BASE + 8) 35 #define GT641XX_TIMER1_IRQ (GT641XX_IRQ_BASE + 9) 36 #define GT641XX_TIMER2_IRQ (GT641XX_IRQ_BASE + 10) 37 #define GT641XX_TIMER3_IRQ (GT641XX_IRQ_BASE + 11) 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 #define GT641XX_PCI_0_MASTER_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 12) 40 #define GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 13) 41 #define GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 14) 42 #define GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 15) 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 #define GT641XX_PCI_0_ADDRESS_ERROR_IRQ (GT641XX_IRQ_BASE + 16) 45 #define GT641XX_MEMORY_ERROR_IRQ (GT641XX_IRQ_BASE + 17) 46 #define GT641XX_PCI_0_MASTER_ABORT_IRQ (GT641XX_IRQ_BASE + 18) 47 #define GT641XX_PCI_0_TARGET_ABORT_IRQ (GT641XX_IRQ_BASE + 19) 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 #define GT641XX_PCI_0_RETRY_TIMEOUT_IRQ (GT641XX_IRQ_BASE + 20) 50 #define GT641XX_CPU_INT0_IRQ (GT641XX_IRQ_BASE + 21) 51 #define GT641XX_CPU_INT1_IRQ (GT641XX_IRQ_BASE + 22) 52 #define GT641XX_CPU_INT2_IRQ (GT641XX_IRQ_BASE + 23) 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 #define GT641XX_CPU_INT3_IRQ (GT641XX_IRQ_BASE + 24) 55 #define GT641XX_CPU_INT4_IRQ (GT641XX_IRQ_BASE + 25) 56 #define GT641XX_PCI_INT0_IRQ (GT641XX_IRQ_BASE + 26) 57 #define GT641XX_PCI_INT1_IRQ (GT641XX_IRQ_BASE + 27) 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 #define GT641XX_PCI_INT2_IRQ (GT641XX_IRQ_BASE + 28) 60 #define GT641XX_PCI_INT3_IRQ (GT641XX_IRQ_BASE + 29) 61 #endif 62
