Lines Matching refs:EXEC
17 /// by writting to the 64-bit EXEC register (each bit corresponds to a
19 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
21 /// EXEC to update the predicates.
33 /// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask
34 /// %SGPR0 = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
38 /// // EXEC are zero.
42 /// %SGPR0 = S_OR_SAVEEXEC_B64 %EXEC // Restore the exec mask for the Then block
43 /// %EXEC = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
48 /// %EXEC = S_OR_B64 %EXEC, %SGPR0 // Re-enable saved exec mask bits
142 .addReg(AMDGPU::EXEC);
158 // If the exec mask is non-zero, skip the next two instructions
161 .addReg(AMDGPU::EXEC);
163 // Exec mask is zero: Export to NULL target...
189 .addReg(AMDGPU::EXEC)
205 .addReg(Src); // Saved EXEC
207 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
208 .addReg(AMDGPU::EXEC)
224 .addReg(AMDGPU::EXEC)
265 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC)
266 .addReg(AMDGPU::EXEC)
271 .addReg(AMDGPU::EXEC);
282 TII->get(AMDGPU::S_OR_B64), AMDGPU::EXEC)
283 .addReg(AMDGPU::EXEC)
307 // Clear this thread from the exec mask if the operand is negative
309 // Constant operand: Set exec mask to 0 or do nothing
312 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
350 // Save the EXEC mask
352 .addReg(AMDGPU::EXEC);
368 // Update EXEC, save the original EXEC value to VCC
375 // Update EXEC, switch all done bits to 0 and all todo bits to 1
376 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
377 .addReg(AMDGPU::EXEC)
383 .addReg(AMDGPU::EXEC);
385 // Restore EXEC
386 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
546 AMDGPU::EXEC).addReg(AMDGPU::EXEC);
