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    Searched defs:Latency (Results 1 - 10 of 10) sorted by null

  /external/llvm/lib/CodeGen/
TargetSchedule.cpp 26 cl::desc("Use TargetSchedModel for latency lookup"));
29 cl::desc("Use InstrItineraryData for latency lookup"));
92 // The machine model may explicitly specify an invalid latency, which
93 // effectively means infinite latency. Since users of the TargetSchedule API
94 // don't know how to handle this, we convert it to a very large latency that is
175 // No operand latency was found.
178 // Expected latency is the max of the stage latency and itinerary props.
179 // Rather than directly querying InstrItins stage latency, we call a TII
180 // hook to allow subtargets to specialize latency. This hook is onl
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MachineScheduler.cpp     [all...]
  /external/llvm/include/llvm/MC/
MCInstrItineraries.h 156 /// getStageLatency - Return the total stage latency of the given
157 /// class. The latency is the maximum completion time for any stage
168 unsigned Latency = 0, StartCycle = 0;
171 Latency = std::max(Latency, StartCycle + IS->getCycles());
174 return Latency;
215 /// getOperandLatency - Compute and return the use operand latency of a given
  /external/llvm/lib/MC/MCDisassembler/
Disassembler.cpp 173 /// \brief Gets latency information for \p Inst form the itinerary
175 /// \return The maximum expected latency over all the operands or -1
191 int Latency = 0;
194 Latency = std::max(Latency, IID.getOperandCycle(SCClass, OpIdx));
196 return Latency;
199 /// \brief Gets latency information for \p Inst, based on \p DC information.
200 /// \return The maximum expected latency over all the definitions or -1
223 // Compute output latency.
224 int Latency = 0
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  /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/
qos.h 36 ULONG Latency;
poclass.h 245 ULONG Latency;
  /external/llvm/include/llvm/CodeGen/
ScheduleDAG.h 89 /// Latency - The time associated with this edge. Often this is just
90 /// the value of the Latency field of the predecessor, however advanced
92 unsigned Latency;
111 Latency = 0;
115 Latency = 1;
120 : Dep(S, Order), Contents(), Latency(0) {
124 /// Return true if the specified SDep is equivalent except for latency.
139 return overlaps(Other) && Latency == Other.Latency;
146 /// getLatency - Return the latency value for this edge, which roughl
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  /external/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 112 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
131 if (Latency < 0)
132 Latency = getInstrLatency(ItinData, DefMI);
150 Latency += 2;
155 return Latency;
614 // an open question. On the A2, the isel instruction has a 2-cycle latency
747 // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
749 // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
753 // lower-latency form is preferable.
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  /external/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp     [all...]
  /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/ddk/
wmidata.h     [all...]

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