| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrBuilder.h | 31 const MCInstrDesc &MCID = MI->getDesc();
33 if (MCID.mayLoad())
35 if (MCID.mayStore())
|
| /external/chromium_org/third_party/skia/experimental/PdfViewer/pdfparser/native/pdfapi/ |
| SkPdfMarkedContentReferenceDictionary_autogen.cpp | 59 int64_t SkPdfMarkedContentReferenceDictionary::MCID(SkPdfNativeDoc* doc) {
60 SkPdfNativeObject* ret = get("MCID", "");
68 return get("MCID", "") != NULL;
|
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 22 const MCInstrDesc &MCID = MI->getDesc();
23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
26 unsigned Opcode = MCID.getOpcode();
43 const MCInstrDesc &MCID = MI->getDesc();
44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
|
| Thumb1RegisterInfo.cpp | 239 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
241 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)
289 const MCInstrDesc &MCID = TII.get(ExtraOpc);
290 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
317 const MCInstrDesc &MCID = TII.get(ARM::tRSB);
318 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
|
| MLxExpansionPass.cpp | 187 const MCInstrDesc &MCID = MI->getDesc();
188 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
191 unsigned Opcode = MCID.getOpcode();
344 const MCInstrDesc &MCID = MI->getDesc();
352 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
362 if (!TII->isFpMLxInstruction(MCID.getOpcode(),
|
| Thumb2ITBlockPass.cpp | 142 const MCInstrDesc &MCID = MI->getDesc();
144 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
|
| ARMBaseRegisterInfo.cpp | 595 const MCInstrDesc &MCID = TII.get(ADDriOpc);
596 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
598 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
|
| Thumb2SizeReduction.cpp | 213 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) {
214 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
549 const MCInstrDesc &MCID = MI->getDesc();
550 if (MCID.hasOptionalDef() &&
551 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
698 const MCInstrDesc &MCID = MI->getDesc();
699 if (MCID.hasOptionalDef()) {
700 unsigned NumOps = MCID.getNumOperands();
726 unsigned NumOps = MCID.getNumOperands();
728 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCInst.h | 24 // MCID is set during instruction lowering.
27 const MCInstrDesc *MCID;
34 MCInst(), MCID(nullptr), packetStart(0), packetEnd(0) {};
35 HexagonMCInst(const MCInstrDesc& mcid):
36 MCInst(), MCID(&mcid), packetStart(0), packetEnd(0) {};
50 void setDesc(const MCInstrDesc& mcid) { MCID = &mcid; };
51 const MCInstrDesc& getDesc(void) const { return *MCID; };
[all...] |
| /external/skia/experimental/PdfViewer/pdfparser/native/pdfapi/ |
| SkPdfMarkedContentReferenceDictionary_autogen.cpp | 59 int64_t SkPdfMarkedContentReferenceDictionary::MCID(SkPdfNativeDoc* doc) {
60 SkPdfNativeObject* ret = get("MCID", "");
68 return get("MCID", "") != NULL;
|
| /external/llvm/lib/CodeGen/ |
| ScoreboardHazardRecognizer.cpp | 129 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
130 if (!MCID) {
134 unsigned idx = MCID->getSchedClass();
185 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
186 assert(MCID && "The scheduler must filter non-machineinstrs");
187 if (DAG->TII->isZeroCost(MCID->Opcode))
194 unsigned idx = MCID->getSchedClass();
|
| ExecutionDepsFix.cpp | 505 const MCInstrDesc &MCID = MI->getDesc();
507 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
|
| PeepholeOptimizer.cpp | 606 const MCInstrDesc &MCID = MI->getDesc();
607 if (MCID.getNumDefs() != 1)
626 const MCInstrDesc &MCID = MI->getDesc();
629 if (MCID.getNumDefs() != 1)
[all...] |
| RegAllocFast.cpp | 806 const MCInstrDesc &MCID = MI->getDesc();
[all...] |
| TargetInstrInfo.cpp | 42 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
45 if (OpNum >= MCID.getNumOperands())
48 short RegClass = MCID.OpInfo[OpNum].RegClass;
49 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
123 const MCInstrDesc &MCID = MI->getDesc();
124 bool HasDef = MCID.getNumDefs();
186 const MCInstrDesc &MCID = MI->getDesc();
187 if (!MCID.isCommutable())
191 SrcOpIdx1 = MCID.getNumDefs();
221 const MCInstrDesc &MCID = MI->getDesc()
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 153 const MCInstrDesc &MCID = MI->getDesc();
155 if (MCID.mayLoad())
157 if (MCID.mayStore())
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 320 const MCInstrDesc &MCID = MIB->getDesc();
321 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
322 MCID.OpInfo[IIOpNum].isOptionalDef();
357 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
[all...] |
| ScheduleDAGFast.cpp | 258 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
259 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
260 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
265 if (MCID.isCommutable())
436 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
437 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
438 unsigned NumRes = MCID.getNumDefs();
439 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
514 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
515 if (!MCID.ImplicitDefs
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.cpp | 294 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
297 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
300 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
|
| AArch64ConditionalCompares.cpp | 593 const MCInstrDesc &MCID = TII->get(Opc);
596 MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF));
598 BuildMI(*Head, Head->end(), TermDL, MCID)
605 TII->getRegClass(MCID, 1, TRI, *MF));
650 const MCInstrDesc &MCID = TII->get(Opc);
652 TII->getRegClass(MCID, 0, TRI, *MF));
655 TII->getRegClass(MCID, 1, TRI, *MF));
657 BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID)
|
| AArch64InstrInfo.cpp | 731 const MCInstrDesc &MCID = get(NewOpc);
732 CmpInstr->setDesc(MCID);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 102 const MCInstrDesc &MCID = get(Opc);
103 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
32 if (!MCID)
35 if (!MCID->mayLoad())
57 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
58 if (!MCID)
61 if (!MCID->isBranch())
87 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID,
92 unsigned IIC = MCID->getSchedClass();
125 if (NSlots == 1 && PPC::getNonRecordFormOpcode(MCID->getOpcode()) != -1)
149 const MCInstrDesc *MCID = DAG->getInstrDesc(SU)
[all...] |
| PPCRegisterInfo.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 71 const MCInstrDesc *MCID; // Instruction descriptor.
113 MachineInstr(MachineFunction&, const MCInstrDesc &MCID,
266 const MCInstrDesc &getDesc() const { return *MCID; }
270 int getOpcode() const { return MCID->Opcode; }
384 return hasProperty(MCID::Variadic, Type);
390 return hasProperty(MCID::HasOptionalDef, Type);
397 return hasProperty(MCID::Pseudo, Type);
401 return hasProperty(MCID::Return, Type);
405 return hasProperty(MCID::Call, Type);
412 return hasProperty(MCID::Barrier, Type)
[all...] |
