| /external/clang/lib/Lex/ |
| PPExpressions.cpp | 600 unsigned ShAmt = static_cast<unsigned>(RHS.Val.getLimitedValue());
602 Overflow = ShAmt >= LHS.Val.getBitWidth();
604 ShAmt = LHS.Val.getBitWidth()-1;
605 Res = LHS.Val << ShAmt;
607 Res = llvm::APSInt(LHS.Val.sshl_ov(ShAmt, Overflow), false);
613 unsigned ShAmt = static_cast<unsigned>(RHS.Val.getLimitedValue());
614 if (ShAmt >= LHS.getBitWidth())
615 Overflow = true, ShAmt = LHS.getBitWidth()-1;
616 Res = LHS.Val >> ShAmt;
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 373 Constant *ShAmt = ConstantExpr::getZExt(COp1, TrOp->getType());
375 Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName());
701 unsigned ShAmt = Op1C->getZExtValue();
706 APInt::getHighBitsSet(Op1C->getBitWidth(), ShAmt))) {
713 ComputeNumSignBits(I.getOperand(0)) > ShAmt) {
743 unsigned ShAmt = Op1C->getZExtValue();
753 isPowerOf2_32(BitWidth) && Log2_32(BitWidth) == ShAmt) {
763 MaskedValueIsZero(Op0,APInt::getLowBitsSet(Op1C->getBitWidth(),ShAmt))){
786 unsigned ShAmt = Op1C->getZExtValue();
807 MaskedValueIsZero(Op0,APInt::getLowBitsSet(Op1C->getBitWidth(),ShAmt))){
[all...] |
| InstCombineMulDivRem.cpp | [all...] |
| InstCombineAddSub.cpp | [all...] |
| InstCombineAndOrXor.cpp | [all...] |
| InstCombineCasts.cpp | [all...] |
| InstCombineCompares.cpp | [all...] |
| /external/llvm/lib/Analysis/ |
| ValueTracking.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 515 SDValue Lo, Hi, ShAmt;
518 ShAmt = DAG.getConstant(BitOffset, TLI.getShiftAmountTy(WideVT));
519 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
528 ShAmt = DAG.getConstant(SrcEltBits - Offset,
530 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
547 ShAmt = DAG.getConstant(WideBits - SrcEltBits,
549 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
550 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
[all...] |
| TargetLowering.cpp | 604 unsigned ShAmt = SA->getZExtValue();
608 if (ShAmt >= BitWidth)
611 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
616 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
619 int Diff = ShAmt-C1;
633 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
643 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
646 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
650 TLO.DAG.getConstant(ShAmt, ShTy))
[all...] |
| SelectionDAG.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/IR/ |
| ConstantFold.cpp | 256 unsigned ShAmt = Amt->getZExtValue();
258 if ((ShAmt & 7) != 0)
260 ShAmt >>= 3;
263 if (ByteStart >= CSize-ShAmt)
267 if (ByteStart+ByteSize+ShAmt <= CSize)
268 return ExtractConstantBytes(CE->getOperand(0), ByteStart+ShAmt, ByteSize);
278 unsigned ShAmt = Amt->getZExtValue();
280 if ((ShAmt & 7) != 0)
282 ShAmt >>= 3;
285 if (ByteStart+ByteSize <= ShAmt)
[all...] |
| /external/llvm/include/llvm/IR/ |
| IRBuilder.h | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 95 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
457 unsigned ShAmt) {
464 (ShAmt == 2 || (Subtarget->isSwift() && ShAmt == 1));
584 unsigned ShAmt = Log2_32(RHSC);
586 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
612 unsigned ShAmt = 0;
622 ShAmt = Sh->getZExtValue();
623 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
626 ShAmt = 0
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| ScalarReplAggregates.cpp | [all...] |
| SROA.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
